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complete thermal system management controller adm1026 rev. a information furnished by analog devices is believed to be a ccurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to chan ge without notice. no license is granted by implication or otherwise under any patent or patent ri ghts of analog devices. trademarks and registered trademarks are the prop erty of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.326.8703 ? 2004 analog devices, inc. all rights reserved. features up to 19 analog measurement channels (including internal measurements) up to 8 fan speed measurement channels up to 17 general-purpose logic i/o pins remote temperature measurement with remote diode (two channels) on-chip temperature sensor analog and pwm fan speed control outputs 2-wire serial system management bus (smbus) 8 kb on-chip eeprom full smbus 1.1 support includes packet error checking (pec) chassis intrusion detection interrupt output (smbalert) reset input, reset outputs thermal interrupt ( therm ) output limit comparison of all monitored values applications network servers and personal computers telecommunications equipment test equipment and measuring instruments d2?/a in9 (0v ? +2.5v) d2+/ a in8 (0v ? +2.5v) a in7 (0v ? +2.5v) a in6 (0v ? +2.5v) to gpio registers 100k ? 100k ? v cc v cc v cc fan speed counter input attenuators and analog multiplexer gpio registers serial bus interface address pointer register band gap temperature sensor automatic fan speed control 8k bytes eeprom 8-bit adc band gap reference v bat +5 v in ?12 v in +12 v in +v ccp a in0 (0v ? +3v) a in1 (0v ? +3v) a in2 (0v ? +3v) a in3 (0v ? +3v) a in4 (0v ? +3v) a in5 (0v ? +3v) d1+ d1?/ntestin dgnd dac agnd v ref (1.82v or 2.5v) scl sda 3.3v main add/ ntestout fan7/gpio7 fan6/gpio6 fan5/gpio5 fan4/gpio4 fan3/gpio3 fan2/gpio2 fan1/gpio1 fan0/gpio0 gpio15 gpio14 gpio13 gpio12 gpio11 gpio10 gpio9 gpio8 pwm 3.3v stby gpio16/therm ci adm1026 int reset in v cc v cc 100k ? resetmain resetstby pwm register and controller limit comparators int mask registers interrupt masking configuration registers value and limit registers 3.3v main reset generator 3.3v stby reset generator interrupt status registers analog output register and 8-bit dac 02657-a-001 figure 1. functional block diagram
adm1026 rev. a | page 2 of 56 table of contents specifications..................................................................................... 3 absolute maximum ratings............................................................ 5 thermal characteristics .............................................................. 5 esd caution.................................................................................. 5 pin configuration and function descriptions............................. 6 typical performance characteristics ............................................. 8 product description....................................................................... 10 functional description.............................................................. 10 internal registers........................................................................ 11 eeprom ..................................................................................... 11 smbus protocols for ram and eeprom .............................. 13 measurement inputs .................................................................. 16 temperature measurement system.......................................... 20 analog output ............................................................................ 22 fan speed measurement ........................................................... 25 enabling and clearing interrupts ............................................ 29 nand tree tests........................................................................ 31 using the adm1026 .................................................................. 33 registers........................................................................................... 36 detailed register descriptions ................................................. 38 outline dimensions ....................................................................... 54 ordering guide .......................................................................... 55 revision history 3/04data sheet changed from rev. 0 to rev. a updated format..................................................................universal change to footnote 4, table 1..........................................................4 added figure 15.................................................................................9 changes to table 6.......................................................................... 17 changes to figure 27...................................................................... 18 change to figure 31 ....................................................................... 19 change to battery measurement input section ......................... 19 changes to table 7.......................................................................... 21 changes to equations in fan speed measurement section...... 26 change to chassis intrusion input section ................................ 27 changes to reset input and outputs section ............................. 31 changes to software reset function section ............................. 34 changes to ordering guide .......................................................... 55 5/02revision 0: initial version
adm1026 rev. a | page 3 of 56 specifications 1, 2, 3 table 1. t a = t min to t max , v cc = v min to v max , unless otherwise noted. parameter min typ max test conditions/comments unit power supply supply voltage, 3.3 v stby, 3.3 v main 3.0 3.3 5.5 v supply current, i cc 2.5 4.0 interface inactive, adc active ma temperature-to-digital converter internal sensor accuracy 3 c resolution 1 c external diode sensor accuracy 3 0c < t d < 100c c resolution 1 c remote sensor source current 90 high level a 5.5 low level a analog-to-digital converter (including mux and attenuators) total unadjusted error (tue) 4 2 % differential nonlinearity (dnl) 1 lsb power supply sensitivity 0.1 %/v conversion time (analog inp ut or internal temperature) 5 11.38 12.06 ms conversion time (external temperature) 5 34.13 36.18 ms input resistance (+5 v in , v ccp , a in0 ? a in5 ) 80 100 120 k? input resistance of +12 v in pin 70 100 115 k? input resistance of ?12 v in pin 8 10 12 k? input resistance (a in6 ? a in9 ) 5 m? input resistance of v bat pin 4 80 100 120 k? v bat current drain (when measured) 80 100 cr2032 battery life >10 years na v bat current drain (when not measured) 6 na analog output (dac) output voltage range 0C2.5 v total unadjusted error (tue) 5 i l = 2 ma % zero error 1 no load lsb differential nonlinearity (dnl) 1 monotonic by design lsb integral nonlinearity 0.5 lsb output source current 2 ma output sink current 1 ma reference output output voltage 1.8 1.82 1.84 bit 2 of register 07h = 0 v output voltage 2.47 2.50 2.53 bit 2 of register 07h = 1 v load regulation (i sink = 2 ma) 0.15 % load regulation (i source = 2 ma) 0.15 % short circuit current 25 v cc = 3.3 v ma output current source 2 ma output current sink 2 ma fan rpm-to-digital converter 6 accuracy 12 % full-scale count 255 fan0 to fan7 nominal input rpm 5 8800 divisor = 1, fan count = 153 rpm 4400 divisor = 2, fan count = 153 rpm 2200 divisor = 4, fan count = 153 rpm 1100 divisor = 8, fan count = 153 rpm internal clock frequency 20 22.5 25 khz open drain o/ps, pwm, gpio0 to 16 output high voltage, v oh 2.4 i out = 3.0 ma, v cc = 3.3 v v
adm1026 rev. a | page 4 of 56 parameter min typ max test conditions/comments unit high level output leakage current, i oh 0.1 1 v out = v cc a output low voltage, v ol 0.4 i out = ?3.0 ma, v cc = 3.3 v v pwm output frequency 75 hz digital outputs (int , resetmain , resetby ) output low voltage, v ol 0.4 i out = ?3.0 ma, v cc = 3.3 v v reset pulse width 140 180 240 ms open drain serial databus output (sda) output low voltage, v ol 0.4 i out = C3.0 ma, v cc = 3.3 v v high level output leakage current, i oh 0.1 1 v out = v cc a serial bus digital inputs (scl, sda) input high voltage, v ih 2.2 v input low voltage, v il 0.8 v hysteresis 500 mv digital input logic levels (add, ci, fan 0 to 7, gpio 0 to 16) 7, 8 input high voltage, v ih 2.4 v cc = 3.3 v v input low voltage, v il 0.8 v cc = 3.3 v v hysteresis (fan 0 to 7) 250 v cc = 3.3 v mv resetmain , resetstby resetmain threshold 2.89 2.94 2.97 falling voltage v resetsby threshold 3.01 3.05 3.10 falling voltage v resetmain hysteresis 60 mv resetstby hysteresis 70 mv digital input current input high current, i ih C1 v in = v cc a input low current, i il 1 v in = 0 a input capacitance, c in 20 pf eeprom reliability endurance 9 100 700 kcycles data retention 10 10 years serial bus timing see figure 2 for all parameters. clock frequency, f sclk 400 khz glitch immunity, t sw 50 ns bus free time, t buf 4.7 s start setup time, t su; sta 4.7 s start hold time, t hd; sta 4 s scl low time, t low 4.7 s scl high time, t high 4 s scl, sda rise time, t r 1000 ns scl, sda fall time, t f 300 ns data setup time, t su; dat 250 ns data hold time, t hd; dat 300 ns 1 all voltages are measured with respect to gnd, unless otherwise specified. 2 typicals are at t a = 25c and represent the most likely parametric norm. shutdown current typ is measured with v cc = 3.3 v. 3 timing specifications are tested at logic levels of v il = 0.8 v for a falling edge and v ih = 2.1 v for a rising edge. 4 total unadjusted error (tue) includes offset, gain, and linearity errors of the adc, multiplexer, and on-chip input attenuator s. v bat is accurate only for v bat voltages greater than 1.5 v (see figure 15). 5 total analog monitoring cycle time is nominally 273 ms, made up of 18 ms 11.38 ms measur ements on analog input and internal temperature channels, and 2 ms 34.13 ms measurements on external temperature channels. 6 the total fan count is based on two pulses per revolution of the fan tachometer output. the total fan monitoring time depends on the number of fans connected and the fan speed. see the fan speed measurement section for more details. 7 add is a three-state input that may be pulled high, low, or left open-circuit. 8 logic inputs accept input high voltages up to 5 v even when device is operating at supply voltages below 5 v. 9 endurance is qualified to 100,000 cycles as per jedec std. 22 method a117, and me asured at ?40c, +25c, and +85c. typical en durance at +25c is 700,000 cycles. 10 retention lifetime equivalent at junction temperature (t j ) = 55c as per jedec std. 22 method a117. retentio n lifetime based on an ac tivation energy of 0.6 v derates with junction temperature as shown in figure 16.
adm1026 rev. a | page 5 of 56 absolute maximum ratings table 2. parameter rating positive supply voltage (v cc ) 6.5 v voltage on +12 v v in pin +20 v voltage on ?12 v v in pin ?20 v voltage on analog pins ?0.3 v to (v cc + 0.3 v) voltage on open drain digital pins ?0.3 v to +6.5 v input current at any pin 5 ma package input current 20 ma maximum junction temperature (t j max ) 150c storage temperature range ?65c to +150c lead temperature, soldering vapor phase (60 sec) 215c infrared (15 sec) 200c esd rating, ?12 v in pin 1000 v esd rating, all other pins 2000 v stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal characteristics ? 48-lead lqfp package ? ja = 50c/w, jc = 10c/w p s t su; dat t high t f t hd; dat t r t low t su; sto ps scl sda t buf t hd; sta t hd; sta t su; sta 02657-a-002 figure 2. serial bus timing diagram esd caution esd (electrostatic discharge) sensitive device. electros tatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge wi thout detection. although this product features proprietary esd protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
adm1026 rev. a | page 6 of 56 pin configuration and fu nction descriptions 36 35 34 33 32 31 30 29 28 27 26 25 48 47 46 45 44 43 42 41 40 39 38 37 13 14 15 16 17 18 19 20 21 22 23 24 adm1026 top view (not to scale) pin 1 identifier gpio9 gpio8 fan0/gpio0 fan1/gpio1 fan2/gpio2 fan3/gpio3 3.3v main dgnd fan4/gpio4 fan5/gpio5 fan6/gpio6 fan7/gpio7 scl sda add/ntestout ci int pwm resetstby resetmain agnd 3.3v stby dac v ref a in5 (0v ? 3v) a in6 (0v ? 2.5v) a in7 (0v ? 2.5v) +v ccp +12 v in ?12 v in +5 v in v bat d2+/a in8 (0v ? 2.5v) d2?/a in9 (0v ? 2.5v) d1+ d1?/ntestin gpio10 gpio11 gpio12 gpio13 gpio14 gpio15 gpio16/therm a in0 (0v ? 3v) a in1 (0v ? 3v) a in2 (0v ? 3v) a in3 (0v ? 3v) a in4 (0v ? 3v) 1 2 3 4 5 6 7 8 9 10 11 12 02657-a-003 figure 3. pin configuration table 3. pin no. mnemonic type description 1 gpio9 digital i/o 1 general-purpose i/o pin that can be conf igured as digital inputs or outputs. 2 gpio8 digital i/o 1 general-purpose i/o pin that can be co nfigured as digital inputs or outputs. 3 fan0/gpio0 digital i/o fan tachometer input with internal 10 k? pull-up resistor to 3.3 v stby. can be reconfigured as a general-purpose, open drain, digital i/o pin. 4 fan1/gpio1 digital i/o fan tachometer input with internal 10 k? pull-up resistor to 3.3 v stby. can be reconfigured as a general-purpose, open drain, digital i/o pin. 5 fan2/gpio2 digital i/o fan tachometer input with internal 10 k? pull-up resistor to 3.3 v stby. can be reconfigured as a general-purpose, open drain, digital i/o pin. 6 fan3/gpio3 digital i/o fan tachometer input with internal 10 k? pull-up resistor to 3.3 v stby. can be reconfigured as a general-purpose, open drain, digital i/o pin. 7 3.3 v main analog input mo nitors the main 3.3 v system suppl y. does not power the device. 8 dgnd ground ground pin for digital circuits. 9 fan4/gpio4 digital i/o fan tachometer input with internal 10 k? pull-up resistor to 3.3 v stby. can be reconfigured as a general-purpose, open drain, digital i/o pin. 10 fan5/gpio5 digital i/o fan tachometer input with internal 10 k? pull-up resistor to 3.3 v stby. can be reconfigured as a general-purpose, open drain, digital i/o pin. 11 fan6/gpio6 digital i/o fan tachometer input with internal 10 k? pull-up resistor to 3.3 v stby. can be reconfigured as a general-purpose, open drain, digital i/o pin. 12 fan7/gpio7 digital i/o fan tachometer input with internal 10 k? pull-up resistor to 3.3 v stby. can be reconfigured as a general-purpose, open drain, digital i/o pin. 13 scl digital input open drain serial bus clock. requires a 2.2 k? pull-up resistor. 14 sda digital i/o serial bus data. open drain i/o. requires a 2.2 k? pull-up resistor. 15 add/ntestout digital input this is a three-state input that controls the tw o lsbs of the serial bus address. it also functions as the output for nand tree testing. 16 ci digital input an active high input that captures a chassis in trusion event in bit 6 of status register 4. this bit remains set until cleared, as lo ng as battery voltage is applied to the v bat input, even when the adm1026 is powered off. 17 int digital output interrupt request (open drain). the output is enabled when bit 1 of the configuration register is set to 1. the defaul t state is disabled. it has an on-chip 100 k? pull-up resistor.
adm1026 rev. a | page 7 of 56 pin no. mnemonic type description 18 pwm digital output open drain pulse width modulated output for co ntrol of the fan speed. this pin defaults to high for the 100% duty cycle for use with nmos drive circuitry. if a pmos device is used to drive the fan, the pwm output may be inverte d by setting bit 1 of test register 1 = 1. 19 resetstby digital output power-on reset. 5 ma driver (weak 100 k? pull-up), active low output (100 k? pull-up) with a 180 ms typical pulse width. resetstby is asserted whenever 3.3 v stby is below the reset threshold. it remains asserted fo r approximately 180 ms after 3.3 v stby rises above the reset threshold. 20 resetmain digital i/o power-on reset. 5 ma driver (weak 100 k? pull-up), active low output (100 k? pull-up) with a 180 ms typical pulse width. resetmain is asserted whenever 3.3 v main is below the reset threshold. it remains asserted fo r approximately 180 ms after 3.3 v main rises above the reset threshold. if, however, 3.3 v st by rises with or before 3.3 v main, then resetmain remains asserted for 180 ms after resetstby is deasserted. pin 20 also functions as an active low reset input. 21 agnd ground ground pin for analog circuits. 22 3.3 v stby power supply supplies 3.3 v powe r. also monitors the 3.3 v standby power rail. 23 dac analog output 0 v to 2.5 v outp ut for analog control of the fan speed. 24 v ref analog output reference volt age output. can be selected as 1.8 v (default) or 2.5 v. 25 d1C/ntestin analog input connected to a cathode of the first remote temper ature sensing diode. if it is held high at power-on, it activates the nand tree test mode. 26 d1+ analog input connected to the anode of the first remote temperature sensing diode. 27 d2C/a in9 programmable connected to the cathode of the second re mote temperature sensing diode, or the analog input may be reconfigured as a 0 v? 2.5 v analog input. 28 d2+/a in8 programmable connected to the anode of the second remote temperature sensing diode, or the analog input may be reconfigured as a 0 v ? 2.5 v analog input. 29 v bat analog input monitors batte ry voltage, nominally +3 v. 30 +5 v in analog input monito rs the +5 v supply. 31 ? 12 v in analog input monitors the ? 12 v supply. 32 +12 v in analog input monito rs the +12 v supply. 33 +v ccp analog input monitors the proces sor core voltage (0 v to 3.0 v). 34 a in7 analog input general-purpos e 0 v to 2.5 v analog inputs. 35 a in6 analog input general-purpos e 0 v to 2.5 v analog inputs. 36 a in5 analog input general-pur pose 0 v to 3 v analog inputs. 37 a in4 analog input general-pur pose 0 v to 3 v analog inputs. 38 a in3 analog input general-pur pose 0 v to 3 v analog inputs. 39 a in2 analog input general-pur pose 0 v to 3 v analog inputs. 40 a in1 analog input general-pur pose 0 v to 3 v analog inputs. 41 a in0 analog input general-pur pose 0 v to 3 v analog inputs. 42 gpio16/therm digital i/o 1 general-purpose i/o pin that can be configured as a digital input or output. can also be configured as a bidirectional therm pin (100 k? pull-up). 43 gpio15 digital i/o 1 general-purpose i/o pin that can be configured as a digital input or output. 44 gpio14 digital i/o 1 general-purpose i/o pin that can be configured as a digital input or output. 45 gpio13 digital i/o 1 general-purpose i/o pin that can be configured as a digital input or output. 46 gpio12 digital i/o 1 general-purpose i/o pin that can be configured as a digital input or output. 47 gpio11 digital i/o 1 general-purpose i/o pin that can be configured as a digital input or output. 48 gpio10 digital i/o 1 general-purpose i/o pin that can be configured as a digital input or output. 1 gpio pins are open drain and require external pull-up resistors. fan inputs have integrated 10 k? pull-ups, but these pins bec ome open drain when reconfigured as gpios.
adm1026 rev. a | page 8 of 56 typical performance characteristics leakage resistance (m ? ) temperature error (c) 10 0 ?20 90 ?25 ?10 d+ to v cc d+ to gnd 30 60 120 0 ?15 ?5 5 15 25 20 02657-a-004 figure 4. temperature error vs. pcb track resistance frequency (mhz) temperature error (c) 12 10 8 6 4 2 0 0 14 100mv 250mv 100 200 300 400 500 600 02657-a-005 figure 5. temperature error vs. power supply noise frequency frequency (mhz) temperature error (c) 0 200 300 400 500 600 0 2 4 8 10 12 6 100 100mv 60mv 40mv 02657-a-006 figure 6. temperature error vs. common-mode noise frequency piii temperature (c) reading (c) 0 10 20 30 40 50 60 70 80 90 100 110 0 10 20 30 40 50 60 70 80 90 100 110 02657-a-007 figure 7. pentium? iii temperature vs. adm1026 reading capacitance (nf) temperature error (c) 5 01020304050 ?10 0 ?5 ?15 ?20 ?25 02657-a-008 figure 8. temperature error vs. capacitance between d+ and dC frequency (mhz) temperature error (c) 100 80 600 70 60 50 40 30 20 10 0 200 300 400 500 100mv 60mv 40mv 02657-a-009 figure 9. temperature error vs. differential-mode noise frequency
adm1026 rev. a | page 9 of 56 temperature (c) reset timeout (ms) ?20 400 80 350 300 250 200 150 100 50 0 0204060 ?40 100 120 450 140 02657-a-010 figure 10. power-up rese t timeout vs. temperature v cc (v) i dd (ma) 3.0 2.5 2.0 1.5 1.0 0.5 3.00 4.00 3.25 3.50 3.75 4.25 4.50 4.75 5.25 5.00 0 5.50 02657-a-011 figure 11. supply current vs. supply voltage temperature (c) temperature error (c) 0.2 0 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 10 20 30 40 50 60 70 80 90 100 110 120 0 02657-a-012 figure 12. local sensor temperature error temperature (c) temperature error (c) 0 0.5 10 20 30 40 50 60 70 80 90 100 110 120 0 1.0 ?0.5 ?1.0 ?1.5 ?2.0 02657-a-013 figure 13. remote sensor temperature error time (s) temperature (c) 4 2 0 20 40 60 80 100 120 068101214161820222426 02657-a-014 figure 14. response to thermal shock 0 0.5 1.0 2.5 3.0 1.5 2.0 3.5 01234 v bat voltage v bat measurement 02657-a-015 figure 15. v bat measurement vs. voltage
adm1026 rev. a | page 10 of 56 product description the adm1026 is a complete system hardware monitor for microprocessor-based systems, providing measurement and limit comparison of various system parameters. the adm1026 has up to 19 analog measurement channels. fifteen analog voltage inputs are provided, five of which are dedicated to monitoring +3.3 v, +5 v, and 12 v power supplies, and the processor core voltage. the adm1026 can monitor two other power supply voltages by measuring its own v cc and the main system supply. one input (two pins) is dedicated to a remote temperature-sensing diode. two additional pins can be configured as general-purpose analog inputs to measure 0 v to 2.5 v, or as a second temperature sensing input. the eight remaining inputs are general-purpose analog inputs with a range of 0 v to 2.5 v or 0 v to 3 v. the adm1026 also has an on-chip temperature sensor. the adm1026 has eight pins that can be configured for fan speed measurement or as general-purpose logic i/o pins. another eight pins are dedicated to general-purpose logic i/o. an additional pin can be configured as a general-purpose i/o or as the bidirectional therm pin. measured values can be read out via a 2-wire serial system management bus, and values for limit comparisons can be programmed over the same serial bus. the high speed, successive approximation adc allows frequent sampling of all analog channels to ensure a fast interrupt response to any out- of-limit measurement. functional description the adm1026 is a complete system hardware monitor for microprocessor-based systems. the device communicates with the system via a serial system management bus. the serial bus controller has a hardwired address line for device selection (add, pin 15), a serial data line for reading and writing addresses and data (sda, pin 14), and an input line for the serial clock (scl, pin 13). all control and programming functions of the adm1026 are performed over the serial bus. measurement inputs programmability of the analog and digital measurement inputs makes the adm1026 extremely flexible and versatile. the device has an 8-bit a/d converter, and 17 analog measurement input pins that can be configured in different ways. pins 25 and 26 are dedicated temperature inputs and may be connected to the cathode and anode of a remote temperature- sensing diode. pins 27 and 28 may be configured as temperature inputs and connected to a second temperature-sensing diode, or may be reconfigured as analog inputs with a range of 0 v to 2.5 v. pins 29 to 33 are dedicated analog inputs with on-chip attenuators configured to monitor v bat , +5 v, ?12 v, +12 v, and the processor core voltage v ccp , respectively. pins 34 to 41 are general-purpose analog inputs with a range of 0 v to 2.5 v or 0 v to 3 v. these are mainly intended for monitoring scsi termination voltages, but may be used for other purposes. the adc also accepts input from an on-chip band gap temperature sensor that monitors system ambient temperature. in addition, the adm1026 monitors the supply from which it is powered, 3.3 v stby, so there is no need for a separate pin to monitor the power supply voltage. the adm1026 has eight pins that are general-purpose logic i/o pins (pins 1, 2, and 43 to 48), a pin that can be configured as gpio or as a bidirectional thermal interrupt ( therm ) pin (pin 42), and eight pins that can be configured for fan speed measurement or as general-purpose logic pins (pins 3 to 6 and pins 9 to 12). sequential measurement when the adm1026 monitoring sequence is started, it cycles sequentially through the measurement of analog inputs and the temperature sensor, while at the same time the fan speed inputs are independently monitored. measured values from these inputs are stored in value registers. these can be read over the serial bus, or can be compared with programmed limits stored in the limit registers. the results of out-of-limit comparisons are stored in the interrupt status registers. an out-of-limit event generates an interrupt on the int line (pin 17). any or all of the interrupt status bits can be masked by appropriate programming of the interrupt mask registers. chassis intrusion a chassis intrusion input (pin 16) is provided to detect unauthorized tampering with the equipment. this event is latched in a battery-backed register bit. resets the adm1026 has two power-on reset outputs, resetmain and resetstby , that are asserted when 3.3 v main or 3.3 v stby fall below the reset threshold. these give a 180 ms reset pulse at power-up. resetmain also functions as an active-low reset input.
adm1026 rev. a | page 11 of 56 fan speed control outputs the adm1026 has two outputs intended to control fan speed, though they can also be used for other purposes. pin 18 is an open drain, pulse width modulated (pwm) output with a programmable duty cycle and an output frequency of 75 hz. pin 23 is connected to the output of an on-chip, 8-bit, digital-to- analog converter with an output range of 0 v to 2.5 v. either or both of these outputs may be used to implement a temperature-controlled fan by controlling the speed of a fan using the temperature measured by the on-chip temperature sensor or remote temperature sensors. internal registers table 4 describes the principal registers of the adm1026. for more detailed information, see table 11 to table 124. table 4. principal registers type description address pointer contains the address that selects one of the other internal registers. when writing to the adm1026, the fi rst byte of data is always a register address, and is written to the address pointer register. configuration registers provide control and configuration for various operating parameters. fan divisor registers contain counter prescaler values for fan speed measurement. dac/pwm control registers contain speed values for pwm and dac fan drive outputs. gpio configuration registers configure the gpio pins as input or output and for signal polarity. value and limit registers store the results of analog voltage inputs, temperature, and fan speed measurements, along with their limit values. status registers store events from the various interrupt sources. mask registers allow masking of individual interrupt sources. eeprom the adm1026 has 8 kb of nonvolatile, electrically erasable, programmable read-only memory (eeprom) from register addresses 8000h to 9fffh. this may be used for permanent storage of data that is not lost when the adm1026 is powered down, unlike the data in the volatile registers. although referred to as read-only memory, the eeprom can be written to (as well as read from) via the serial bus in exactly the same way as the other registers. the main differences between the eeprom and other registers are ? an eeprom location must be blank before it can be written to. if it contains data, it must first be erased. ? writing to eeprom is slower than writing to ram. ? writing to the eeprom should be restricted because its typical cycle life is 100,000 write operations, due to the usual eeprom wear-out mechanisms. the eeprom in the adm1026 has been qualified for two key eeprom memory characteristics: memory cycling endurance and memory data retention. endurance qualifies the ability of the eeprom to be cycled through many program, read, and erase cycles. in real terms, a single endurance cycle is composed of four independent, sequential events, as follows: 1. initial page erase sequence 2. read/verify sequence 3. program sequence 4. second read/verify sequence in reliability qualification, every byte is cycled from 00h to ffh until a first fail is recorded, signifying the endurance limit of the eeprom memory. retention quantifies the ability of the memory to retain its programmed data over time. the eeprom in the adm1026 has been qualified in accordance with the formal jedec retention lifetime specification (a117) at a specific junction temperature (t j = 55c) to guarantee a minimum of 10 years retention time. as part of this qualification procedure, the eeprom memory is cycled to its specified endurance limit described above before data retention is characterized. this means that the eeprom memory is guaranteed to retain its data for its full specified retention lifetime every time the eeprom is reprogrammed. note that retention lifetime based on an activation energy of 0.6 v derates with t j , as shown in figure 16. junction temperature (c) 250 retention (years) 300 100 200 150 50 0 50 60 70 80 90 100 40 110 120 02657-a-016 figure 16. typical eeprom memory retention
adm1026 rev. a | page 12 of 56 serial bus interface control of the adm1026 is carried out via the serial system management bus (smbus). the adm1026 is connected to this bus as a slave device, under the control of a master device. the adm1026 has a 7-bit serial bus slave address. when the device is powered on, it does so with a default serial bus address. the 5 msbs of the address are set to 01011, and the 2 lsbs are determined by the logical states of pin 15 add/ntestout. this pin is a three-state input that can be grounded, connected to v cc , or left open-circuit to give three different addresses. table 5. address pin truth table add pin a1 a0 gnd 0 0 no connect 1 0 v cc 0 1 if add is left open-circuit, the default address is 0101110 (5ch). add is sampled only at power-up on the first valid smbus transaction, so any changes made while the power is on (and the address is locked) have no effect. the facility to make hardwired changes to device addresses allows the user to avoid conflicts with other devices sharing the same serial bus, for example if more than one adm1026 is used in a system. general smbus timing figure 17 and figure 18 show timing diagrams for general read and write operations using the smbus. the smbus specification defines specific conditions for different types of read and write operations, which are discussed later in this section. the general smbus protocol 1 operates as follows: 1. the master initiates data transfer by establishing a start condition, defined as a high-to-low transition on the serial data line (sda) while the serial clock line scl remains high. this indicates that a data stream follows. all slave peripherals connected to the serial bus respond to the start condition and shift in the next 8 bits, consisting of a 7-bit slave address (msb first) and an r/ w bit, which determine the direction of the data transfer, that is, whether data is written to or read from the slave device (0 = write, 1 = read). the peripheral whose address corresponds to the trans- mitted address responds by pulling the data line low during the low period before the ninth clock pulse, known as the acknowledge bit, and holding it low during the high period of this clock pulse. all other devices on the bus remain idle while the selected device waits for data to be read from or written to it. if the r/ w bit is 0, the master writes to the slave device. if the r/ w bit is 1, the master reads from the slave device. 2. data is sent over the serial bus in sequences of nine clock pulses, 8 bits of data followed by an acknowledge bit from the slave device. data transitions on the data line must occur during the low period of the clock signal and re- main stable during the high period, because a low-to-high transition when the clock is high may be interpreted as a stop signal. if the operation is a write operation, the first data byte after the slave address is a command byte. this tells the slave device what to expect next. it may be an instruction telling the slave device to expect a block write, or it may simply be a register address that tells the slave where subsequent data is to be written. because data can flow in only one direction as defined by the r/ w bit, it is not possible to send a command to a slave device during a read operation. before doing a read oper- ation, it may first be necessary to do a write operation to tell the slave what type of read operation to expect and/or the address from which data is to be read. 3. when all data bytes have been read or written, stop conditions are established. in write mode, the master pulls the data line high during the 10th clock pulse to assert a stop condition. in read mode, the master device releases the sda line during the low period before the ninth clock pulse, but the slave device does not pull it low (called no acknowledge). the master takes the data line low during the low period before the 10th clock pulse, then high during the 10th clock pulse to assert a stop condition. 1 if it is required to pe rform several read or write operations in succession, the master can send a repeat st art condition instead of a stop condition to begin a new operation.
adm1026 rev. a | page 13 of 56 r/w 0 scl sda 10 1 1 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 ack. by slave start by master frame 1 slave address frame 2 command code 191 ack. by slave 9 d7 d6 d5 d4 d3 d2 d1 d0 ack. by slave stop by master frame n data byte 19 9 scl (continued) sda (continued) d7 d6 d5 d4 d3 d2 d1 d0 ack. by slave frame 3 data byte 1 02657-a-017 figure 17. general smbus write timing diagram r/w 0 scl sda 10 1 1 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 ack. by master start by master frame 1 slave address frame 2 data byte 191 ack. by slave 9 d7 d6 d5 d4 d3 d2 d1 d0 no ack. stop by master frame n data byte 19 9 scl (continued) sda (continued) d7 d6 d5 d4 d3 d2 d1 d0 ack. by master frame 3 data byte 1 02657-a-018 figure 18. general smbus read timing diagram smbus protocols for ram and eeprom the adm1026 contains volatile registers (ram) and non- volatile eeprom. ram occupies addresses 00h to 6fh, while eeprom occupies addresses 8000h to 9fffh. data can be written to and read from both ram and eeprom as single data bytes and as block (sequential) read or write operations of 32 data bytes, the maximum block size allowed by the smbus specification. data can only be written to unprogrammed eeprom locations. to write new data to a programmed location, it is first necessary to erase it. eeprom erasure cannot be done at the byte level; the eeprom is arranged as 128 pages of 64 bytes, and an entire page must be erased. note that of these 128 pages, only 124 pages are available to the user. the last four pages are reserved for manufacturing purposes and cannot be erased/rewritten. the eeprom has three ram registers associated with it, eeprom registers 1, 2, and 3 at addresses 06h, 0ch, and 13h. eeprom registers 1 and 2 are for factory use only. eeprom register 3 sets up the eeprom operating mode. setting bit 0 of eeprom register 3 puts the eeprom into read mode. setting bit 1 puts it into programming mode. setting bit 2 puts it into erase mode. only one of these bits must be set before the eeprom may be accessed. setting no bits or more than one of them causes the device to respond with no acknowledge if an eeprom read, program, or erase operation is attempted. it is important to distinguish between smbus write opera- tions, such as sending an address or command, and eeprom programming operations. it is possible to write an eeprom address over the smbus, whatever the state of eeprom register 3. however, eeprom register 3 must be correctly set before a subsequent eeprom operation can be performed. for example, when reading from the eeprom, bit 0 of eeprom register 3 can be set, even though smbus write operations are required to set up the eeprom address for reading.
adm1026 rev. a | page 14 of 56 bit 3 of eeprom register 3 is used for eeprom write protec- tion. setting this bit prevents accidental programming or era- sure of the eeprom. if an eeprom write or erase operation is attempted when this bit is set, the adm1026 responds with no acknowledge. this bit is write-once and can only be cleared by a power-on reset. eeprom register 3 bit 7 is used for clock extend. program- ming an eeprom byte takes approximately 250 s, which would limit the smbus clock for repeated or block write opera- tions. because eeprom block read/write access is slow, it is recommended that this clock extend bit typically be set to 1. this allows the adm1026 to pull scl low and extend the clock pulse when it cannot accept any more data. adm1026 smbus operations the smbus specification defines several protocols for different types of read and write operations. the ones used in the adm1026 are discussed below. the following abbreviations are used in the diagrams: s start w write p stop a acknowledge r read a no acknowledge adm1026 write operations send byte in this operation, the master device sends a single command byte to a slave device, as follows: 1. the master device asserts a start condition on the sda. 2. the master sends the 7-bit slave address followed by the write bit (low). 3. the addressed slave device asserts an ack on the sda. 4. the master sends a command code. 5. the slave asserts ack on the sda. 6. the master asserts a stop condition on the sda and the transaction ends. in the adm1026, the send byte protocol is used to write a register address to ram for a subsequent single-byte read from the same address or block read or write starting at that address. this is illustrated in figure 19. s slave address w ram address (00h to 6fh) a ap 12 3 4 56 02657-a-019 figure 19. setting a ram address for subsequent read if it is required to read data from the ram immediately after setting up the address, the master can assert a repeat start condition immediately after the final ack and carry out a single byte read, block read, or block write operation without asserting an intermediate stop condition. write byte/word in this operation, the master device sends a command byte and one or two data bytes to the slave device as follows: 1. the master device asserts a start condition on the sda. 2. the master sends the 7-bit slave address followed by the write bit (low). 3. the addressed slave device asserts an ack on the sda. 4. the master sends a command code. 5. the slave asserts an ack on the sda. 6. the master sends a data byte. 7. the slave asserts an ack on the sda. 8. the master sends a data byte (or may assert stop here.) 9. the slave asserts an ack on the sda. 10. the master asserts a stop condition on the sda to end the transaction. in the adm1026, the write byte/word protocol is used for four purposes. the adm1026 knows how to respond by the value of the command byte and eeprom register 3. the first purpose is to write a single byte of data to ram. in this case, the command byte is the ram address from 00h to 6fh and the (only) data byte is the actual data. this is illustrated in figure 20. s slave address wa ram address (00h to 6fh) 12 3 4 56 a data ap 78 02657-a-020 figure 20. single byte write to ram the protocol is also used to set up a 2-byte eeprom address for a subsequent read or block read. in this case, the command byte is the high byte of the eeprom address from 80h to 9fh. the (only) data byte is the low byte of the eeprom address. this is illustrated in figure 21. s slave address w eeprom address high byte (80h to 9fh) 13456 a a 7 a 2 p 8 eeprom address low byte (00h to ffh) 02657-a-021 figure 21. setting an eeprom address if it is required to read data from the eeprom immediately after setting up the address, the master can assert a repeat start condition immediately after the final ack and carry out a single-byte read or block read operation without asserting an intermediate stop condition. in this case, bit 0 of eeprom register 3 should be set. the third use is to erase a page of eeprom memory. eeprom memory can be written to only if it is previously erased. before writing to one or more eeprom memory locations that are already programmed, the page or pages containing those locations must first be erased. eeprom memory is erased by writing an eeprom page address plus an arbitrary byte of data with bit 2 of eeprom register 3 set to 1.
adm1026 rev. a | page 15 of 56 because the eeprom consists of 128 pages of 64 bytes, the eeprom page address consists of the eeprom address high byte (from 80h to 9fh) and the two msbs of the low byte. the lower six bits of the eeprom address (low byte only) specify addresses within a page and are ignored during an erase operation. s slave address wa eeprom address high byte (80h to 9fh) 12 3 4 5 6 a a arbitrary data 78 eeprom address low byte (00h to ffh) ay 9 10 02657-a-022 figure 22. eeprom page erasure page erasure takes approximately 20 ms. if the eeprom is accessed before erasure is complete, the adm1026 responds with no acknowledge. last, this protocol is used to write a single byte of data to eeprom. in this case, the command byte is the high byte of the eeprom address from 80h to 9fh. the first data byte is the low byte of the eeprom address, and the second data byte is the actual data. bit 1 of eeprom register 3 must be set. this is illustrated in figure 23. s slave address wa eeprom address high byte (80h to 9fh) 12 3 4 5 6 a a data 78 eeprom address low byte (00h to ffh) ay 910 02657-a-023 figure 23. single-byte write to eeprom block write in this operation, the master device writes a block of data to a slave device. the start address for a block write must have been set previously. in the case of the adm1026, this is done by a send byte operation to set a ram address or by a write byte/word operation to set an eeprom address. 1. the master device asserts a start condition on the sda. 2. the master sends the 7-bit slave address followed by the write bit (low). 3. the addressed slave device asserts an ack on the sda. 4. the master sends a command code that tells the slave device to expect a block write. the adm1026 command code for a block write is a0h (10100000). 5. the slave asserts an ack on the sda. 6. the master sends a data byte (20h) that tells the slave device that 32 data bytes are being sent to it. the master should always send 32 data bytes to the adm1026. 7. the slave asserts an ack on the sda. 8. the master sends 32 data bytes. 9. the slave asserts an ack on the sda after each data byte. 10. the master sends a packet error checking (pec ) byte. 11. the adm1026 checks the pec byte and issues an ack if correct. if incorrect (nack), the master resends the data bytes. 12. the master asserts a stop condition on the sda to end the transaction. s slave address wa command a0h block write a a data 1 byte count aa ap data 2 a data 32 pec 02857-a-024 figure 24. block write to eeprom or ram when performing a block write to eeprom, bit 1 of eeprom register 3 must be set. unlike some eeprom devices that limit block writes to within a page boundary, there is no limitation on the start address when performing a block write to eeprom, except: ? there must be at least 32 locations from the start address to the highest eeprom address (9fff) to avoid writing to invalid addresses. ? if the addresses cross a page boundary, both pages must be erased before programming. adm1026 read operations the adm1026 uses the smbus read protocols described here. receive byte in this operation, the master device receives a single byte from a slave device as follows: 1. the master device asserts a start condition on the sda. 2. the master sends the 7-bit slave address followed by the read bit (high). 3. the addressed slave device asserts an ack on the sda. 4. the master receives a data byte. 5. the master asserts a no ack on the sda. 6. the master asserts a stop condition on the sda to end the transaction. in the adm1026, the receive byte protocol is used to read a single byte of data from a ram or eeprom location whose address has previously been set by a send byte or write byte/word operation. figure 25 shows this. when reading from eeprom, bit 0 of eeprom register 3 must be set. s slave address ra data a p 12 3456 02657-a-025 figure 25. single-byte read from eeprom or ram
adm1026 rev. a | page 16 of 56 block read in this operation, the master device reads a block of data from a slave device. the start address for a block read must have been set previously. in the case of the adm1026 this is done by a send byte operation to set a ram address, or by a write byte/word operation to set an eeprom address. the block read operation consists of a send byte operation that sends a block read command to the slave, immediately followed by a repeated start and a read operation that reads out multiple data bytes as follows: 1. the master device asserts a start condition on the sda. 2. the master sends the 7-bit slave address followed by the write bit (low). 3. the addressed slave device asserts an ack on the sda. 4. the master sends a command code that tells the slave device to expect a block read. the adm1026 command code for a block read is a1h (10100001). 5. the slave asserts an ack on the sda. 6. the master asserts a repeat start condition on the sda. 7. the master sends the 7-bit slave address followed by the read bit (high). 8. the slave asserts an ack on the sda. 9. the adm1026 sends a byte count data byte that tells the master how many data bytes to expect. the adm1026 always returns 32 data bytes (20h), the maximum allowed by the smbus 1.1 specification. 10. the master asserts an ack on the sda. 11. the master receives 32 data bytes. 12. the master asserts an ack on the sda after each data byte. 13. the adm1026 issues a pec byte to the master. the master should check the pec byte and issue another block read if the pec byte is incorrect. 14. a nack is generated after the pec byte to signal the end of the read. 15. the master asserts a stop condition on the sda to end the transaction. s slave address wa command a1h block read a s r a p data 32 pec a a byte count a data 1 a slave address 02657-a-026 figure 26. block read from eeprom or ram when block reading from eeprom, bit 0 of eeprom register 3 must be set. note that although the adm1026 supports packet error checking (pec), its use is optional. the pec byte is calculated using crc-8. the frame check sequence (fcs) conforms to crc-8 by the polynomial: c(x) = x 8 + x 2 + x 1 + 1 consult the smbus 1.1 specification for more information. measurement inputs the adm1026 has 17 external analog measurement pins that can be configured to perform various functions. it also meas- ures two supply voltages, 3.3 v main and 3.3 v stby, and the internal chip temperature. pins 25 and 26 are dedicated to remote temperature measure- ment, while pins 27 and 28 can be configured as analog inputs with a range of 0 v to 2.5 v, or as inputs for a second remote temperature sensor. pins 29 to 33 are dedicated to measuring v bat , + 5 v, ? 1 2 v, +12 v supplies, and the processor core voltage v ccp. the remaining analog inputs, pins 34 to 41, are general-purpose analog inputs with a range of 0 v to 2.5 v (pins 34 and 35) or 0 v to 3 v (pins 36 to 41). a-to-d converter (adc) these inputs are multiplexed into the on-chip, successive approximation, analog-to-digital converter. the adc has a resolution of 8 bits. the basic input range is 0 v to 2.5 v, which is the input range of a in6 to a in9 , but five of the inputs have built-in attenuators to allow measurement of v bat , +5 v, ? 12 v, +12 v, and the processor core voltage v ccp , without any external components. to allow the tolerance of these supply voltages, the adc produces an output of 3/4 full scale (decimal 192) for the nominal input voltage, and so has adequate headroom to cope with over voltages. table 6 shows the input ranges of the analog inputs and output codes of the adc. when the adc is running, it samples and converts an analog or local temperature input every 711 s (typical value). each input is measured 16 times and the measurements are averaged to reduce noise, so the total conversion time for each input is 11.38 ms. measurements on the remote temperature (d1 and d2) inputs take 2.13 ms. these are also measured 16 times and are averaged, so the total conversion time for a remote temperature input is 34.13 ms.
adm1026 rev. a | page 17 of 56 table 6. a-to-d output code vs. v in input voltage a-to-d output +12 v in C12 v in +5 v in 3.3 v main 3.3 v stby v bat 1 v ccp a in (0C5) a in (6C9) decimal binary < 0.0625 < -15.928 < 0.026 < 0.0172 na < 0.012 < 0.012 < 0.010 0 00000000 0.062-0.125 ? 15.928-15.855 0.026-0.052 0.017-0.034 na 0.012-0.023 0.012-0.023 0.010-0.019 1 00000001 0.125-0.187 ? 15.855-15.783 0.052-0.078 0.034-0.052 na 0.023-0.035 0.023-0.035 0.019-0.029 2 00000010 0.188-0.250 ? 15.783-15.711 0.078-0.104 0.052-0.069 na 0.035-0.047 0.035-0.047 0.029-0.039 3 00000011 0.250-0.313 ? 15.711-15.639 0.104-0.130 0.069-0.086 na 0.047-0.058 0.047-0.058 0.039-0.049 4 00000100 0.313-0.375 ? 15.639-15.566 0.130-0.156 0.086-0.103 na 0.058-0.070 0.058-0.070 0.049-0.058 5 00000101 0.375-0.438 ? 15.566-15.494 0.156-0.182 0.103-0.120 na 0.070-0.082 0.070-0.082 0.058-0.068 6 00000110 0.438-0.500 ? 15.494-15.422 0.182-0.208 0.120-0.138 na 0.082-0.094 0.082-0.094 0.068-0.078 7 00000111 0.500-0.563 ? 15.422-15.349 0.208-0.234 0.138-0.155 na 0.094-0.105 0.094-0.105 0.078-0.087 8 00001000 ? ? ? 4.000-4.063 ? 11.375-11.303 1.667-1.693 1.110-1.127 na 0.750-0.780 0.750-0.780 0.625-0.635 64 (1?4 scale) 01000000 ? ? ? 8.000-8.063 ? 6.750?6.678 3.333-3.359 2.000-2.016 2.000-2.016 1.500-1.512 1.500-1.512 1.250-1.260 128 (1?2 scale) 10000000 ? ? ? 12.000-12.063 ? 2.125-2.053 5-5.026 3.330-3.347 3.000-3.016 2.250-2.262 2.250-2.262 1.875-1.885 192 (3?4 scale) 11000000 ? ? ? 15.313-15.375 1.705-1.777 6.38-6.406 4.249-4.267 3.828- 3.844 2.871-2.883 2.871-2.883 2.392-2.402 245 11110101 15.375-15.437 1.777-1.850 6.406-6.432 4.267-4.284 3.844- 3.860 2.883-2.895 2.883-2.895 2.402-2.412 246 11110110 15.437-15.500 1.850-1.922 6.432-6.458 4.284-4.301 3.860- 3.875 2.895-2.906 2.895-2.906 2.412-2.422 247 11110111 15.500-15.563 1.922-1.994 6.458-6.484 4.301-4.319 3.875- 3.890 2.906-2.918 2.906-2.918 2.422-2.431 248 11111000 15.562-15.625 1.994-2.066 6.484-6.51 4.319-4.336 3.890- 3.906 2.918-2.930 2.918-2.930 2.431-2.441 249 11111001 15.625-15.688 2.066-2.139 6.51-6.536 4.336-4.353 3.906- 3.921 2.930-2.941 2.930-2.941 2.441-2.451 250 11111010 15.688-15.750 2.139-2.211 6.536-6.563 4.353-4.371 3.921- 3.937 2.941-2.953 2.941-2.953 2.451-2.460 251 11111011 15.750-15.812 2.211-2.283 6.563-6.589 4.371-4.388 3.937- 3.953 2.953-2.965 2.953-2.965 2.460-2.470 252 11111100 15.812-15.875 2.283-2.355 6.589-6.615 4.388-4.405 3.953- 3.969 2.965-2.977 2.965-2.977 2.470-2.480 253 11111101 15.875-15.938 2.355-2.428 6.615-6.641 4.405-4.423 3.969- 3.984 2.977-2.988 2.977-2.988 2.480-2.490 254 11111110 >15.938 >2.428 >6.634 >4.423 >3.984 >2.988 >2.988 >2.490 255 11111111 1 v bat is not accurate for voltag es under 1.5 v (see figure 15).
adm1026 rev. a | page 18 of 56 voltage measurement inputs the internal structure for all the analog inputs is shown in figure 27. each input circuit consists of an input protection diode, an attenuator, plus a capacitor to form a first-order low- pass filter that gives each voltage measurement input immunity to high frequency noise. the ?12 v input also has a resistor connected to the on-chip reference to offset the negative voltage range so that it is always positive and can be handled by the adc. this allows most popular power supply voltages to be monitored directly by the adm1026 without requiring any additional resistor scaling. 109.4k ? 18.5pf 21.9k +v ccp 9.3pf v ref 17.5k ? 114.3k ? ?12v 49.5k ? 82.7k ? 4.5pf v bat * see text a in0 ? a in5 (0v ? 3v) 109.4k ? 4.6pf 21.9k ? a in6 ? a in9 (0v ? 2.5v) 4.6pf 52.5k ? 50k ? 4.6pf 83.5k ? +5v 21k ? 9.3pf 113.5k ? +12v mux 02657-a-027 figure 27. voltage measurement inputs setting other input ranges a in0 to a in9 can easily be scaled to voltages other than 2.5 v or 3 v. if the input voltage range is zero to some positive voltage, all that is required is an input attenuator, as shown in figure 28. r1 r2 v in a in(0?9) 02657-a-028 figure 28. scaling a in0 ? a in9 however, when scaling a in0 to a in5 , it should be noted that these inputs already have an on-chip attenuator, because their primary function is to monitor scsi termination voltages. this attenuator loads any external attenuator. the input resistance of the on-chip attenuator can be between 100 k? and 200 k?. for this tolerance not to affect the accuracy, the output resistance of the external attenuator should be very much lower than this, that is, 1 k? in order to add not more than 1% to the total unadjusted error (tue). alternatively, the input can be buffered using an op amp. ( ) () in5 in0 fs a a v r2 r1 to for 0 . 3 0 . 3 ? = ( ) () in9 in6 fs a a v r2 r1 to for 5 . 2 5 . 2 ? = negative and bipolar input ranges can be accommodated by using a positive reference voltage to offset the input voltage range so that it is always positive. to monitor a negative input voltage, an attenuator can be used as shown in figure 29. r1 r2 v in a in(0?9) 02657-a-029 figure 29. scaling and offsetting a in0 ? a in9 for negative inputs this offsets the negative voltage so that the adc always sees a positive voltage. r1 and r2 are chosen so that the adc input voltage is zero when the negative input voltage is at its maximum (most negative) value, that is: os fs v v r2 r1 ? = this is a simple and low cost solution, but note the following: ? because the input signal is offset but not inverted, the input range is transposed. an increase in the magnitude of the negative voltage (going more negative) causes the input voltage to fall and give a lower output code from the adc. conversely, a decrease in the magnitude of the negative voltage causes the adc code to increase. the maximum negative voltage corresponds to zero output from the adc. this means that the upper and lower limits are transposed. ? for the adc output to be full scale when the negative voltage is zero, v os must be greater than the full-scale voltage of the adc, because v os is attenuated by r1 and r2. if v os is equal to or less than the full-scale voltage of the adc, the input range is bipolar but not necessarily symmetrical. this is a problem only if the adc output must be full scale when the negative voltage is zero.
adm1026 rev. a | page 19 of 56 symmetrical bipolar input ranges can be accommodated easily by making v os equal to the full-scale voltage of the analog input, and by adding a third resistor to set the positive full scale. r1 r2 v in a in(0?9) r3 +v os 02657-a-030 figure 30. scaling and offsetting a in0 ? a in9 for bipolar inputs os fs v v r2 r1 ? = note that r3 has no effect as the input voltage at the device pin is zero when v in = negative full scale. ( ) () in5 in0 fs a a v r3 r1 to for 0 . 3 0 . 3 ? = ( ) () in9 in6 fs a a v r3 r1 to for 5 . 2 5 . 2 ? = also, note that r2 has no effect as the input voltage at the device pin is equal to v os when v in = positive full scale. battery measurement input (v bat ) the v bat input allows the condition of a cmos backup battery to be monitored. this is typically a lithium coin cell such as a cr2032. the v bat input is accurate only for voltages greater than 1.5 v (see figure 15). typically, the battery in a system is required to keep some device powered on when the system is in a powered-off state. the v bat measurement input is specially designed to minimize battery drain. to reduce current drain from the battery, the lower resistor of the v bat attenuator is not connected, except whenever a v bat measurement is being made. the total current drain on the v bat pin is 80 na typical (for a maximum v bat voltage = 4 v), so a cr2032 cmos battery functions in a system in excess of the expected 10 years. note that when a v bat measurement is not being made, the current drain is reduced to 6 na typical. under normal voltage meas- urement operating conditions, all measurements are made in a round-robin format, and each reading is actually the result of 16 digitally averaged measurements. however, averaging is not carried out on the v bat measurement to reduce measurement time and therefore reduce the current drain from the battery. the v bat current drain when a measurement is being made is calculated by period pulse bat t t v i = k 100 for example, when v bat = 3 v, a n 78 ms 273 711 k 100 v 3 = = s i where t pulse = v bat measurement time (711 s typical), t period = time to measure all analog inputs (273 ms typical), and v bat input battery protection. v bat input battery protection in addition to minimizing battery current drain, the v bat measurement circuitry was specifically designed with battery protection in mind. internal circuitry prevents the battery from being back-biased by the adm1026 supply or through any other path under normal operating conditions. in the unlikely event of a catastrophic adm1026 failure, the adm1026 includes a second level of battery protection including a series 3 k? resistor to limit current to the battery, as recommended by ul. thus, it is not necessary to add a series resistor between the battery and the v bat input; the battery can be connected directly to the v bat input to improve voltage measurement accuracy. adc v bat digital control 49.5k ? 82.7k ? 4 .5pf 3k ? 3k ? 02657-a-031 figure 31. equivalent v bat input protection circuit reference output (v ref ) the adm1026 offers an on-chip reference voltage (pin 24) that can be used to provide a 1.82 v or 2.5 v reference voltage out- put. this output is buffered and specified to sink or source a load current of 2 ma. the reference voltage outputs 1.82 v if bit 2 of configuration register 3 (address 07h) is 0; it outputs 2.5 v when this bit is set to 1. this voltage reference output can be used to provide a stable reference voltage to external cir- cuitry such as ldos. the load regulation of the v ref output is typically 0.15% for a sink current of 2 ma and 0.15% for 2 ma source current. there may be some ripple present on the v ref output that requires filtering (4 m v max ). figure 32 shows the recommended circuitry for the v ref output for loads less than 2 ma. for loads in excess of 2 ma, external circuitry, such as that shown in figure 33, can be used to buffer the v ref output. 10k ? 0.1 f v ref adm1026 24 v ref 02657-a-033 figure 32. v ref interface circuit for v ref loads < 2 ma
adm1026 rev. a | page 20 of 56 if the v ref output is not being used, it should be left uncon- nected. do not connect v ref to gnd using a capacitor. the internal output buffer on the voltage reference is capacitively loaded, which can cause the voltage reference to oscillate. this affects temperature readings reported back by the adm1026. the recommended interface circuit for the v ref output is shown in figure 33. 10k ? 0.1 f adm1026 24 +12v 0.1 f 10 f 50 ? v ref ndt3055 v ref 02657-a-034 figure 33. v ref interface circuit for v ref loads > 2 ma temperature measurement system local temperature measurement the adm1026 contains an on-chip band gap temperature sensor whose output is digitized by the on-chip adc. the temperature data is stored in the local temperature value register (address 1fh). as both positive and negative temper- atures can be measured, the temperature data is stored in twos complement format, as shown in table 7. theoretically, the temperature sensor and adc can measure temperatures from ?128c to +127c with a resolution of 1c. temperatures below t min and above t max are outside the operating temperature range of the device, however, so local temperature measure- ments outside this range are not possible. temperature measurement from ?128c to +127c is possible using a remote sensor. remote temperature measurement the adm1026 can measure the temperature of two remote diode sensors, or diode-connected transistors, connected to pins 25 and 26, or 27 and 28. pins 25 and 26 are a dedicated temperature input channel. pins 27 and 28 can be configured to measure a diode sensor by clearing bit 3 of configuration register 1 (address 00h) to 0. if this bit is 1, then pins 27 and 28 are a in8 and a in9 . the forward voltage of a diode or diode-connected transistor, operated at a constant current, exhibits a negative temperature coefficient of about ?2 mv/c. unfortunately, the absolute value of v be varies from device to device, and individual calibration is required to null this out, so the technique is unsuitable for mass production. the technique used in the adm1026 is to measure the change in v be when the device is operated at two different currents, given by () log = where k is boltzmanns constant, q is the charge on the carrier, t is the absolute temperature in kelvins, and n is the ratio of the two currents. figure 34 shows the input signal conditioning used to measure the output of a remote temperature sensor. this figure shows the external sensor as a substrate transistor provided for temperature monitoring on some microprocessors, but it could equally well be a discrete transistor such as a 2n3904. if a discrete transistor is used, the collector is not grounded and should be linked to the base. if a pnp transistor is used, the base is connected to the d? input and the emitter to the d+ input. if an npn transistor is used, the emitter is connected to the d? input and the base to the d+ input. to prevent ground noise from interfering with the measure- ment, the more negative terminal of the sensor is not referenced to ground but is biased above ground by an internal diode at the d? input. to me a su re v be , the sensor is switched between operating currents of i and n i. the resulting waveform is passed through a 65 khz low-pass filter to remove noise, and to a chopper-stabilized amplifier that performs the functions of amplification and rectification of the waveform to produce a dc voltage proportional to v be . this voltage is measured by the adc to give a temperature output in 8-bit, twos complement format. to further reduce the effects of noise, digital filtering is performed by averaging the results of 16 measurement cycles. a remote temperature measurement takes nominally 2.14 ms.
adm1026 rev. a | page 21 of 56 c1* d+ d? remote sensing t ransisto r in i i bias v dd v out+ to adc v out? bias diode low-pass filter f c = 65khz capacitor c1 is optional. it is only necessary in noisy environments. c1 = 2.2nf typical, 3nf max. * 02657-a-032 figure 34. signal conditioning for remote diode temperature sensors the results of external temperature measurements are stored in 8-bit, twos complement format, as illustrated in table 7. table 7. temperature data format temperature digital output hex ?128c 1000 0000 80 ?125c 1000 0011 83 ?100c 1001 1100 9c ?75c 1011 0101 b5 ?50c 1100 1110 ce ?25c 1110 0111 e7 ?10c 11110110 f6 0c 0000 0000 00 10c 0000 1010 0a 25c 0001 1001 19 50c 0011 0010 32 75c 0100 1011 4b 100c 0110 0100 64 125c 0111 1101 7d 127c 0111 1111 7f layout considerations digital boards can be electrically noisy environments. take these precautions to protect the analog inputs from noise, particularly when measuring the very small voltages from a remote diode sensor. ? place the adm1026 as close as possible to the remote sensing diode. provided that the worst noise sources such as clock generators, data/address buses, and crts are avoided, this distance can be 4 to 8 inches. ? route the d+ and d? tracks close together, in parallel, with grounded guard tracks on each side. provide a ground plane under the tracks if possible. ? use wide tracks to minimize inductance and reduce noise pickup. a 10 mil track minimum width and spacing is recommended. 10mil 10mil 10mil 10mil 10mil 10mil 10mil gnd d+ gnd d? 02657-a-035 figure 35. arrangement of signal tracks ? try to minimize the number of copper/solder joints, which can cause thermocouple effects. where copper/solder joints are used, make sure that they are in both the d+ and d? paths and are at the same temperature. ? thermocouple effects should not be a major problem because 1c corresponds to about 240 v, and thermocouple voltages are about 3 v/c of temperature difference. unless there are two thermocouples with a big temperature differential between them, thermocouple voltages should be much less than 200 mv. ? place a 0.1 f bypass capacitor close to the adm1026. ? if the distance to the remote sensor is more than eight inches, the use of twisted-pair cable is recommended. this works from about 6 to 12 feet. ? for very long distances (up to 100 feet), use shielded twisted pair such as belden #8451 microphone cable. connect the twisted pair to d+ and d? and the shield to gnd close to the adm1026. leave the remote end of the shield unconnected to avoid ground loops. because the measurement technique uses switched current sources, excessive cable and/or filter capacitance can affect the measurement. when using long cables, the filter capacitor may be reduced or removed. cable resistance can also introduce errors. a 1 ? series resistance introduces about 0.5c error.
adm1026 rev. a | page 22 of 56 limit values limit values for analog measurements are stored in the appropri ate limit registers. in the case of voltage measurements, high and low limits can be stored so that an interrupt request is generated if the measured value goes above or below acceptable values. in the case of temperature, a hot temperature or high limit can be programmed, and a hot temperature hysteresis or low limit can be programmed, which is usually some degrees lower. this can be useful because it allows the system to be shut down when the hot limit is exceeded, and restarted automatically when it has cooled down to a safe temperature. analog monitoring cycle time the analog monitoring cycle begins when a 1 is written to the start bit (bit 0), and a 0 to the int_clear bit (bit 2) of the con- figuration register. int_enable (bit 1) should be set to 1 to enable the int output. the adc measures each analog input in turn, starting with remote temperature channel 1 and ending with local temperature. as each measurement is completed, the result is automatically stored in the appropriate value register. this round-robin monitoring cycle continues until it is disabled by writing a 0 to bit 0 of the configuration register. because the adc is typically left to free-run in this way, the most recently measured value of any input can be read out at any time. for applications where the monitoring cycle time is important, it can easily be calculated. the total number of channels measured is ? five dedicated supply voltage inputs ? ten general-purpose analog inputs ? 3.3 v main ? 3.3 v stby ? local temperature ? two remote temperature pins 28 and 27 are measured both as analog inputs a in8 /a in9 and as remote temperature input d2+/d2?, irrespective of which configuration is selected for these pins. if pins 28 and 27 are configured as a in8 /a in9 , the measurements for these channels are stored in registers 27h and 29h, and the invalid temperature measurement is discarded. on the other hand, if pins 28 and 27 are configured as d2+/d2?, the temper- ature measurement is stored in register 29h, and there is no valid result in register 27h. as mentioned previously, the adc performs a conversion every 711 s on the analog and local temperature inputs and every 2.13 ms on the remote temperature inputs. each input is measured 16 times and averaged to reduce noise. the total monitoring cycle time for voltage and temperature inputs is therefore nominally (18 16 0.711) + (2 16 2.13) = 273 ms the adc uses the internal 22.5 khz clock, which has a toler- ance of 6%, so the worst-case monitoring cycle time is 290 ms. the fan speed measurement uses a completely separate monitoring loop, as described later. input safety scaling of the analog inputs is performed on-chip, so external attenuators are typically not required. however, because the power supply voltages appear directly at the pins, it is advisable to add small external resistors (that is, 500 ?) in series with the supply traces to the chip to prevent damaging the traces or power supplies should an accidental short such as a probe connect two power supplies together. because the resistors form part of the input attenuators, they affect the accuracy of the analog measurement if their value is too high. the worst such accident would be connecting ?12 v to +12 v where there is a total of 24 v difference. with the series resistors, this would draw a maximum current of approximately 24 ma. analog output the adm1026 has a single analog output from an unsigned 8-bit dac that produces 0 v to 2.5 v (independent of the refer- ence voltage setting). the input data for this dac is contained in the dac control register (address 04h). the dac control register defaults to ffh during a power-on reset, which pro- duces maximum fan speed. the analog output may be amplified and buffered with external circuitry such as an op amp and a transistor to provide fan speed control. during automatic fan speed control, described later, the four msbs of this register set the minimum fan speed. suitable fan drive circuits are shown in figure 36 through figure 40. when using any of these circuits, note the following: ? all of these circuits provide an output range from 0 v to almost +12 v, apart from figure 36, which loses the base- emitter voltage drop of q1 due to the emitter-follower configuration. ? to amplify the 2.5 v range of the analog output up to 12 v, the gain of these circuits needs to be about 4.8. ? take care when choosing the op amp to ensure that its input common-mode range and output voltage swing are suitable. ? the op amp may be powered from the +12 v rail alone or from 12 v. if it is powered from +12 v, the input common-mode range should include ground to accom- modate the minimum output voltage of the dac, and the output voltage should swing below 0.6 v to ensure that the transistor can be turned fully off. ? if the op amp is powered from ?12 v, precautions such as a clamp diode to ground may be needed to prevent the base-emitter junction of the output transistor being reverse-biased in the unlikely event that the output of the op amp should swing negative for any reason.
adm1026 rev. a | page 23 of 56 ? in all these circuits, the output transistor must have an i cmax greater than the maximum fan current, and be capable of dissipating power due to the voltage dropped across it when the fan is not operating at full speed. ? if the fan motor produces a large back emf when switched off, it may be necessary to add clamp diodes to protect the output transistors in the event that the output goes from full scale to zero very quickly. q1 2n2219a dac r1 10k ? 1/4 lm324 r2 36k ? 12v 02657-a-036 figure 36. fan drive circuit with op amp and emitter-follower q1 bd136 2sa968 dac r1 10k ? 1/4 lm324 r2 39k ? r4 1k ? r3 1k ? 12v 02657-a-037 figure 37. fan drive circuit with op amp and pnp transistor q1 irf9620 dac 12v r1 10k ? 1/4 lm324 r2 39k ? r3 100k ? 02657-a-038 figure 38. fan drive circuit with op amp and p-channel mosfet r2 100k ? q1/q2 mbt3904 dual 12v dac r3 39k ? r4 10k ? q3 irf9620 r2 100k ? 02657-a-039 figure 39. discrete fan drive circuit with p-channel mosfet, single supply r2 100k ? q1/q2 mbt3904 dual +12v dac r3 39k ? r4 10k ? r1 4.7k ? ?12v q3 irf9620 02657-a-040 figure 40. discrete fan drive circuit with p-channel mosfet, dual supply pwm output fan speed may also be controlled using pulse width modulation (pwm). the pwm output (pin 18) produces a pulsed output with a frequency of approximately 75 hz and a duty cycle defined by the contents of the pwm control register (address 05h). during automatic fan speed control, described below, the four msbs of this register set the minimum fan speed. the open drain pwm output must be amplified and buffered to drive the fans. the pwm output is intended to be used with an nmos driver, but may be inverted by setting bit 1 of test register 1 (address 14h) if using pmos drivers. figure 41 shows how a fan may be driven under pwm control using an n-channel mosfet. +v q1 ndt3055l pwm 3.3v 10k ? typ 5v or 12v fan 02657-a-041 figure 41. pwm fan drive circuit using an n-channel mosfet
adm1026 rev. a | page 24 of 56 automatic fan speed control the adm1026 offers a simple method of controlling fan speed according to temperature without intervention from the host processor. monitoring must be enabled by setting bit 0 of configuration register 1 (address 00h), to enable automatic fan speed control. automatic fan speed control can be applied to the dac output, the pwm output, or both, by setting bit 5 and/or bit 6 of configuration register 1. the t min registers (addresses 10h to 12h) contain minimum temperature values for the three temperature channels (on-chip sensor and two remote diodes). this is the temperature at which a fan starts to operate when the temperature sensed by the controlling sensor exceeds t min . t min can be the same or different for all three channels. t min is set by writing a twos complement temperature value to the t min registers. if any sensor channel is not required for automatic fan speed control, t min for that channel should be set to 127c (01111111). in automatic fan speed control mode, (as shown figure 42 and figure 43) the four msbs of the dac control register (address 04h) and pwm control register (address 05h) set the minimum values for the dac and pwm outputs. note that, if both dac control and pwm control are enabled (bits 5 and 6 of configuration register 1 = 1), the four msbs of the dac control register (address 04h) define the minimum fan speed values for both the dac and pwm outputs. the value in the pwm control register (address 05h) has no effect. minimum dac code dac min = 16 d 256 5 . 2 code voltage output dac = minimum pwm duty cycle pwmmin = 6.67 d where d is the decimal equivalent of bits 7 to 4 of the register. when the temperature measured by any of the sensors exceeds the corresponding t min , the fan is spun up for 2 seconds with the fan drive set to maximum (full scale from the dac or 100% pwm duty cycle). the fan speed is then set to the minimum as previously defined. as the temperature increases, the fan drive increases until the temperature reaches t min + 20c. the fan drive at any temperature up to 20c above t min is given by () 20 100 min actual min min t t pwm pwm pwm ? ? + = or () 20 240 min actual min min t t dac dac dac ? ? + = for simplicity of the automatic fan speed algorithm, the dac code increases linearly up to 240, not its full scale of 255. however, when the temperature exceeds t min +20c, the dac output jumps to full scale. to ensure that the maximum cooling capacity is always available, the fan drive is always set by the sensor channel demanding the highest fan speed. if the temperature falls, the fan does not turn off until the temperature measured by all three temperature sensors has fallen to their corresponding t min ? 4c. this prevents the fan from cycling on and off continuously when the temperature is close to t min . whenever a fan starts or stops during automatic fan speed control, a one-off interrupt is generated at the int output. this is described in more detail in the section on the adm1026 interrupt structure. pwm o utput min temperature t min spin up for 2 seconds 100% t min ? 4c t min + 20c 02657-a-042 figure 42. automatic pwm fan control transfer function dac o utput min temperature t min 255 t min ? 4c t min + 20c spin up for 2 seconds 240 02657-a-043 figure 43. automatic dac fan control transfer function fan inputs pins 3 to 6 and 9 to 12 may be configured as fan speed measuring inputs by clearing the corresponding bit(s) of configuration register 2 (address 01h), or as general-purpose logic inputs/outputs by setting bits in this register. the power- on default value for this register is 00h, which means all the inputs are set for fan speed measurement.
adm1026 rev. a | page 25 of 56 signal conditioning in the adm1026 accommodates the slow rise and fall times typical of fan tachometer outputs. the fan tach inputs have internal 10 k? pull-up resistors to 3.3 v stby. in the event that these inputs are supplied from fan outputs that exceed the supply, either resistive attenuation of the fan signal or diode clamping must be included to keep inputs within an acceptable range. figure 44 through figure 47 show circuits for common fan tach outputs. if the fan tach output is open-drain or has a resistive pull-up to v cc , then it can be connected directly to the fan input, as shown in figure 44. 12v fan speed counter fan(0?7) pull-up 4.7k ? typ tach output v cc 02657-a-044 figure 44. fan with tach pull-up to +v cc if the fan output has a resistive pull-up to +12 v (or other voltage greater than 3.3 v stby), the fan output can be clamped with a zener diode, as shown in figure 45. the zener voltage should be chosen so that it is greater than v ih but less than 3.3 v stby, allowing for the voltage tolerance of the zener. 12v fan speed counter fan(0?7) pull-up 4.7k ? typ tach output v cc * choose zd1 voltage approximately 0.8 v cc zd1* zener 02657-a-045 figure 45. fan with tach pull-up to voltage > v cc (e.g. 12 v), clamped with zener diode if the fan has a strong pull-up (less than 1 k?) to +12 v, or a totem pole output, a series resistor can be added to limit the zener current, as shown in figure 46. alternatively, a resistive attenuator may be used, as shown in figure 47. r1 and r2 should be chosen such that () < + + < r2 r1 pullup r r2 12v fan speed counter fan(0?7) pull-up typ <1 k ? or totem pole tach output v cc * choose zd1 voltage approximately 0.8 v cc zd1* zener r1 10k ? 02657-a-046 figure 46. fan with strong tach pull-up to > v cc or totem pole output, clamped with zener and resistor 12v fan speed counter fan(0?7) <1 k ? tach output v cc r1* * see text 02657-a-047 figure 47. fan with strong tach pull-up to >v cc or totem pole output, attenuated with r1/r2 fan speed measurement the fan counter does not count the fan tach output pulses directly because the fan speed may be less than 1000 rpm and it would take several seconds to accumulate a reasonably large and accurate count. instead, the period of the fan revolution is measured by gating an on-chip 22.5 khz oscillator into the input of an 8-bit counter for two periods of the fan tach output, as shown in figure 48, so the accumulated count is actually proportional to the fan tach period and inversely proportional to the fan speed. 22.5khz clock configuration reg. 1 bit 0 fan0 input fan0 measurement period fan1 measurement period start of monitoring cycle fan1 input 1 2 34 12 3 4 02657-a-048 figure 48. fan speed measurement the monitoring cycle begins when a 1 is written to the monitor bit (bit 0 of configuration register 1). the int_enable (bit 1) should be set to 1 to enable the int output.
adm1026 rev. a | page 26 of 56 the fan speed counter starts counting as soon as the fan channel has been switched to. if the fan tach count reaches 0xff, the fan has failed or is not connected. if a fan is connected and running, the counter is reset on the second tach rising edge, and oscillator pulses are actually counted from the second rising tach edge to the fourth rising edge. the measurement then switches to the next fan channel. here again, the counter begins counting and is reset on the second tach rising edge, and oscillator pulses are counted from the second rising edge to the fourth rising edge. this is repeated for the other six fan channels. note that fan speed measurement does not occur until 1.8 seconds after the monitor bit has been set. this is to allow the fans adequate time to spin up. otherwise, the adm1026 could generate false fan failure interrupts. during the 1.8 second fan spin-up time, all fan tach registers read 0x00. to accommodate fans of different speed and/or different numbers of output pulses per revolution, a prescaler (divisor) of 1, 2, 4, or 8 may be added before the counter. divisor values for fans 0 to 3 are contained in the fan 0C3 divisor register (address 02h) and those for fans 4 to 7 in the fan 4C7 divisor register (address 03h). the default value is 2, which gives a count of 153 for a fan running at 4400 rpm producing two output pulses per revolution. the count is calculated by the equation: divisor rpm count = 60 10 5 . 22 3 for constant-speed fans, fan failure is typically considered to have occurred when the speed drops below 70% of nominal, corresponding to a count of 219. full scale (255) is reached if the fan speed fell to 60% of its nominal value. for temperature- controlled, variable-speed fans, the situation is different. table 8 shows the relationship between fan speed and time per revolution at 60%, 70%, and 100% of nominal rpm for fan speeds of 1100, 2200, 4400, and 8800 rpm, and the divisor that would be used for each of these fans, based on two tach pulses per revolution. limit values fans generally do not over-speed if run from the correct voltage, so the failure condition of interest is under speed due to electrical or mechanical failure. for this reason, only low speed limits are programmed into the limit registers for the fans. it should be noted that because fan period rather than speed is being measured, a fan failure interrupt occurs when the measurement exceeds the limit value. fan monitoring cycle time the fan speeds are measured in sequence from 0 to 7. the monitoring cycle time depends on the fan speed, the number of tach output pulses per revolution, and the number of fans being monitored. if a fan is stopped or running so slowly that the fan speed counter reaches 255 before the second tach pulse after initializa- tion, or before the fourth tach pulse during measurement, the measurement is terminated. this also occurs if an input is con- figured as gpio instead of fan. any channels connected in this manner time out after 255 clock pulses. the worst-case measurement time for a fan-configured channel occurs when the counter reaches 254 from start to the second tach pulse and reaches 255 after the second tach pulse. taking into account the tolerance of the oscillator frequency, the worst- case measurement time is 509 d 0.05 ms where: 509 is the total number of clock pulses. d is the divisor: 1, 2, 4, or 8. 0.05 ms is the worst-case oscillator period in ms. the worst-case fan monitoring cycle time is the sum of the worst-case measurement time for each fan. although the fan monitoring cycle and the analog input monitoring cycle are started together, they are not synchronized in any other way. table 8. fan speeds and divisors time per divisor rpm nominal rev rpm (ms) 70 rpm rev 70 (ms) 60 rpm rev 60 (ms) 1 8800 6.82 6160 9.74 5280 11.36 2 4400 13.64 3080 19.48 2640 22.73 4 2200 27.27 1540 38.96 1320 45.45 8 1100 54.54 770 77.92 660 90.9
adm1026 rev. a | page 27 of 56 chassis intrusion input the chassis intrusion input is an active high input intended for detection and signaling of unauthorized tampering with the system. when this input goes high, the event is latched in bit 6 of status register 4, and an interrupt is generated. the bit remains set until cleared by writing a 1 to ci clear, bit 1 of configuration register 3 (05h), as long as battery voltage is connected to the v bat input. the ci clear bit itself is cleared by writing a 0 to it. the ci input detects chassis intrusion events even when the adm1026 is powered off (provided battery voltage is applied to v bat ) but does not immediately generate an interrupt. once a chassis intrusion event is detected and latched, an interrupt is generated when the system is powered on. the actual detection of chassis intrusion is performed by an external circuit that detects, for example, when the cover has been removed. a wide variety of techniques may be used for the detection, for example: ? a microswitch that opens or closes when the cover is removed. ? a reed switch operated by magnet fixed to the cover. ? a hall-effect switch operated by magnet fixed to the cover. ? a phototransistor that detects light when the cover is removed. the chassis intrusion input can also be used for other types of alarm input. figure 49 shows a temperature alarm circuit using an ad22105 temperature switch sensor. this produces a low- going output when the preset temperature is exceeded, so the output is inverted by q1 to make it compatible with the ci input. q1 can be almost any small-signal npn transistor, or a ttl or cmos inverter gate may be used if one is available. see the ad22105 data sheet on the analog devices, inc. website (www.analog.com) for information on selecting r set . v cc r set ad22105 temperature sensor 6 ci r1 10k ? q1 7 3 2 1 18 02657-a-049 figure 49. using the ci input with a temperature sensor general-purpose i/o pins (open drain) the adm1026 has eight pins that are dedicated to general- purpose logic input/output (pins 1, 2, and 43 to 48), eight pins that can be configured as general-purpose logic pins or fan speed inputs (pins 3 to 6, and 9 to 12), and one pin that can be configured as gpio16 or the bidirectional therm pin (pin 42). the gpio/fan pins are configured as general- purpose logic pins by setting bits 0 to 7 of configuration register 2 (address 01h). pin 42 is configured as gpio16 by setting bit 0 of configuration register 3, or as the therm function by clearing this bit. each gpio pin has four data bits associated with it, two bits in one of the gpio configuration registers (addresses 08h to 0bh), one in the gpio status registers (addresses 24h and 25h), and one in the gpio mask registers (addresses 1ch and 1dh) setting a direction bit = 1 in one of the gpio configuration registers makes the corresponding gpio pin an output. clearing the direction bit to 0 makes it an input. setting a polarity bit = 1 in one of the gpio configuration registers makes the corresponding gpio pin active high. clearing the polarity bit to 0 makes it active low. when a gpio pin is configured as an input, the corresponding bit in one of the gpio status registers is read-only, and is set when the input is asserted (asserted may be high or low depending on the setting of the polarity bit). when a gpio pin is configured as an output, the corresponding bit in one of the gpio status registers becomes read/write. setting this bit then asserts the gpio output. (here again, asserted may be high or low depending on the setting of the polarity bit.) the effect of a gpio status register bit on the int output can be masked out by setting the corresponding bit in one of the gpio mask registers. when the pin is configured as an output, this bit is automatically masked to prevent the data written to the status bit from causing an interrupt, with the exception of gpio16, which must be masked manually by setting bit 7 of mask register 4 (reg 1bh). when configured as inputs, the gpio pins may be connected to external interrupt sources such as temperature sensors with digital output. another application of the gpio pins would be to monitor a processors voltage id code (vid code).
adm1026 rev. a | page 28 of 56 adm1026 interrupt structure the interrupt structure of the adm1026 is shown in figure 53. interrupts can come from a number of sources, which are com- bined to form a common int output. when int is asserted, this output pulls low. the int pin has an internal, 100 k? pull-up resistor. analog/temperature inputs as each analog measurement value is obtained and stored in the appropriate value register, the value and the limits from the corresponding limit registers are fed to the high and low limit comparators. the device performs greater than comparisons to the high limits. an out-of-limit is also generated if a result is less than or equal to a low limit. the result of each comparison (1 = out of limit, 0 = in limit) is routed to the corresponding bit input of interrupt status register 1, 2, or 4 via a data demultiplexer, and used to set that bit high or low as appro- priate. status bits are self-clearing. if a bit in a status register is set due to an out-of-limit measurement, it continues to cause int to be asserted as long as it remains set, as described later. however, if a subsequent measurement is in limit, it is reset and does not cause int to be reasserted. status bits are unaffected by clearing the interrupt. interrupt mask registers 1, 2, and 4 have bits corresponding to each of the interrupt status register bits. setting an interrupt mask bit high conceals an asserted status bit from display on interrupt pin 17. setting an interrupt mask bit low allows the corresponding status bit to be asserted and displayed on pin 17. after mask gating, the status bits are all ored together to produce the analog and fan interrupt that is used to set a latch. the output of this latch is ored with other interrupt sources to produce the int output. this pulls low if any unmasked status bit goes high, that is, when any measured value goes out of limit. when an int output caused by an out-of-limit analog/ temperature measurement is cleared by one of the methods described later, the latch is reset. it is not set again, and int is not reasserted until after two local temperature measure-ments have been taken, even if the status bit remains set or a new analog/temperature event occurs, as shown in figure 50. this delay corresponds to almost two monitoring cycles, and is about 530 ms. however, interrupts from other sources such as a fan or gpio can still occur. this is illustrated in figure 51. start of analo g monitoring cycle out-of-limit measurement start of analog monitoring cycle int int cleared local temperature measurement start of analog monitoring cycle int re-asserted out-of-limit measurement full monitoring cycle = 273ms temperature local measurement 02657-a-051 figure 50. delay after clearing int before reassertion start of analo g monitoring cycle out-of-limit measurement local tempereature measurement start of analog monitoring cycle local temperature measurement start of analog monitoring cycle int cleared int re-asserted new int from fan new int from gpio gpio de-asserted int int cleared 02657-a-052 figure 51. other interrupt sources can reassert int immediately
adm1026 rev. a | page 29 of 56 status register 4 also stores inputs from two other interrupt sources that operate in a different way from the other status bits. if automatic fan speed control (afc) is enabled, bit 4 of status register 4 is set whenever a fan starts or stops. this bit causes a one-off int output as shown in figure 52. it is cleared during the next monitoring cycle and if int has been cleared, it does not cause int to be reasserted. int int cleared by status regular 1 read, bit 2 of configuration regular 1 set, or ara fan on fan off 02657-a-053 figure 52. assertion of int due to afc event in a similar way, a change of state at the therm output (described in more detail later), sets bit 3 of status register 4 and causes a one-off int output. a change of state at the therm output also causes bit 0 of status register 1, bit 1 of status register 1, or bit 0 of status register 4 to be set, depending on which temperature channel caused the therm event. this bit is reset during the next monitoring cycle, provided the temperature channel is within the normal high and low limits. fan inputs fan inputs generate interrupts in a similar way to analog/ temperature inputs, but as the analog/ temperature inputs and fan inputs have different monitoring cycles, they have separate interrupt circuits. as the speed of each fan is measured, the output of the fan speed counter is stored in a value register. the result is compared to the fan speed limit and is used to set or clear a bit in status register 3. in this case, the fan is monitored only for under-speed (fan counter > fan speed limit). mask register 3 is used to mask fan interrupts. after mask gating, the fan status bits are ored together and used to set a latch, whose output is ored with other interrupt sources to produce the int output. like the analog/temp interrupt, an int output caused by an out-of-limit fan speed measurement, once cleared, is not reasserted until the end of the next monitoring cycle, although other interrupt sources may cause int to be asserted. gpio and ci pins. when gpio pins are configured as inputs, asserting a gpio input (high or low, depending on polarity) sets the corresponding gpio status bit in status registers 5 and 6, or bit 7 of status register 4 (gpio16). a chassis intrusion event sets bit 6 of status register 4. the gpio and ci status bits, after mask gating, are ored together and ored with other interrupt sources to produce the int output. gpio and ci interrupts are not latched and cannot be cleared by normal interrupt clearing. they can only be cleared by masking the status bits or by removing the source of the interrupt. enabling and clearing interrupts the int output is enabled when bit 1 of configuration register 1 (int_enable) is high, and bit 2 (int_clear) is low. int may be cleared if ? status register 1 is read. ideally, if polling the status registers trying to identify interrupt sources, status register 1 should be polled last, because a read of status register 1 clears all the other interrupt status registers. ? the adm1026 receives the alert response address (ara) (0001 100) over the smbus. ? bit 2 of configuration register 1 is set. bidirectional therm pin the adm1026 has a second interrupt pin (gpio16/ therm pin 42) that responds only to critical thermal events. the therm pin goes low whenever a therm limit is exceeded. this function is useful for cpu throttling or system shutdown. in addition, whenever therm is activated, the pwm and dac outputs go full scale to provide fail-safe system cooling. this output is enabled by setting bit 4 of configuration register 1 (register 00h). whenever a therm limit is exceeded, bit 3 of status register 4 (reg 23h) is set, even if the therm function is disabled (bit 4 of configuration register 1 = 0). in this case, the therm status bit is set, but the pwm and dac outputs are not forced to full scale. three thermal limit registers are provided for the three temperature sensors at addresses 0dh to 0fh. these registers are dedicated to the therm function and none of the other limit registers have any effect on the therm output. if any of the temperature measurements exceed the correspond- ing limit, therm is asserted (low) and the dac and pwm outputs go to maximum to drive any cooling fans to full speed. to avoid cooling fans cycling on and off continually when the temperature is close to the limit, a fixed hysteresis of 5c is provided. therm is only deasserted when the measured temperature of all three sensors is 5c below the limit. whenever the therm output changes, int is asserted, as shown in figure 54. however, this is edge-triggered, so if int is subsequently cleared by one of the methods previously described, it is not reasserted, even if therm remains asserted. therm causes int to be reasserted only when it changes state.
adm1026 rev. a | page 30 of 56 1 = out of limit high and low limit comparators int enable int clear int int temp v bat a in8 therm afc reserved ci gpio16 ext1 temp ext 2 temp 3.3v stby 3.3v main +5v v ccp +12v ?12v fan0 fan1 fan2 fan3 fan4 fan5 fan6 fan7 from fan speed value and limit registers high limit comparator data demultiplexer 1 = out of limit value high limit gpio0 to gpio7 gpio8 to gpio15 masking data from smbus masking data from smbus a in0 a in1 a in2 a in3 a in4 a in5 a in6 a in7 high limit low limit value from analog/temp value and limit registers data demultiplexer mask gating 8 status bit mask bit mask data from smbus (same bit names and order as status bits) latch reset in out ci gpio16 mask gating 8 status bit mask bit mask gating 8 status bit mask bit mask gating 8 status bit mask bit mask gating 8 status bit mask bit mask gating 8 status bit mask bit mask register 1 status register 1 0 1 2 3 4 5 6 7 mask register 2 status register 2 0 1 2 3 4 5 6 7 mask register 4 status register 4 0 1 2 3 4 5 6 7 mask register 3 status register 3 0 1 2 3 4 5 6 7 mask data from smbus (same bit names and order as status bits) mask data from smbus (same bit names and order as status bits) mask data from smbus (same bit names and order as status bits) latch reset in out mask register 5 mask register 6 status register 6 status register 5 02657-a-050 figure 53. interrupt structure
adm1026 rev. a | page 31 of 56 note that the therm pin is bidirectional, so therm may be pulled low externally as an input. this causes the pwm and dac outputs to go to full scale until therm is returned high again. to disable therm as an input, set bit 0 of configuration register 3 (reg. 07h). this configures pin 42 as gpio16 and prevents a low on pin 42 from driving the fans at full speed. therm limit therm limit ? 5c therm int int cleared by status reg 1 read, bit 2 of config. reg. 1 set, or ara temperature 02657-a-054 figure 54. assertion of int due to therm event reset input and outputs the adm1026 has two active low, power-on reset outputs, resetmain and resetstby . these operate as follows. resetstby monitors 3.3 v stby. at power-up, resetstby is asserted (pulled low) until 180 ms after 3.3 v stby rises above the reset threshold. resetmain monitors 3.3 v main. this means that at power- up, resetmain is asserted (pulled low) until 180 ms after 3.3 v main rises above the reset threshold. if 3.3 v main rises with or before dv cc , resetmain remains asserted until 180 ms after resetstby is negated. resetmain can also function as a reset input. pulling this pin low resets the registers, which are initialized to their default values by a software reset. (see the software reset function section for register details). note that the 3.3 v stby pin supplies power to the adm1026. in applications that do not require monitoring of a 3.3 v stby and 3.3 v main supply, these two pins should be connected together (3.3 v main should not be left floating). to ensure that the 3.3 v stby pin does not become backdriven, the 3.3 v stby supply should power on before all other voltages in the system. see table 3 for more information about pin configuration. resetstby resetmain 3.3vmain ~1v 180ms power-on reset 180ms 3.3vstby ~1v 02657-a-055 figure 55. operation of offset outputs nand tree tests a nand tree is provided in the adm1026 for automated test equipment (ate) board-level connectivity testing. this allows the functionality of all digital inputs to be tested in a simple manner and any pins that are nonfunctional or shorted together to be identified. the structure of the nand tree is shown in figure 56. the device is placed into nand tree test mode by powering up with pin 25 held high. this pin is sampled automatically after power-up, and if it is connected high, then the nand test mode is invoked. ntestout gpio8 fan0 fan1 fan2 fan3 fan4 fan5 fan6 ci sda scl fan7 int gpio9 gpio10 gpio11 gpio12 gpio13 gpio14 gpio15 gpio16 02657-a-056 figure 56. nand tree the nand tree test may be carried out in one of two ways. 1. start with all inputs low and take them high in turn, starting with the input nearest to ntest_out (gpio16/ therm ) and working back up the tree to the input furthest from ntestout ( int ). this should give the characteristic output pattern shown in figure 57, with ntestout toggling each time an input is taken high. 2. start with all inputs high and take them low in turn, starting with the input furthest from ntest_out ( int ) and working down the tree to the input nearest to ntest_out (gpio16/ therm ). this should give a similar output pattern to figure 58.
adm1026 rev. a | page 32 of 56 notes ? for a nand tree test to work, all outputs ( int , rstmain, rststby, and pwm) must remain high during the test. ? when generating test waveforms, allow for a typical propagation delay of 500 ns through the nand tree. ? if any of the inputs shown in figure 56 are unused, they should not be connected direct to ground, but via a resistor such as 10 k?. this allows the automatic test equipment (ate) to drive every input high so that the nand tree test can be properly carried out. gpio16 gpio15 gpio14 gpio13 gpio12 gpio11 gpio10 gpio9 gpio8 fan0 fan1 fan2 fan3 fan4 fan5 fan6 fan7 scl sda ci int ntestout 02657-a-057 figure 57. nand tree test taking inputs high in turn in the event of an input being nonfunctional (stuck high or low) or two inputs shorted together, the output pattern is different. some examples are given in figure 59 through figure 61. figure 59 shows the effect of one input being stuck low. the output pattern is normal until the stuck input is reached. because that input is permanently low, neither it nor any inputs further up the tree can have any effect on the output. int ci sda scl fan7 fan6 fan5 fan4 fan3 fan2 fan1 fan0 gpio8 gpio9 gpio10 gpio11 gpio12 gpio13 gpio14 gpio15 gpio16 ntestout 02657-a-058 figure 58. nand tree test taking inputs low in turn gpio16 gpio15 gpio14 gpio13 gpio12 gpio11 gpio10 gpio9 gpio8 fan0 fan1 ntestout 02657-a-059 figure 59. nand tree test with gpio11 stuck low
adm1026 rev. a | page 33 of 56 figure 60 shows the effect of one input being stuck high. taking gpio12 high should take the output high. however, the next input up the tree, gpio11, is already high, so the output immediately goes low again, causing a missing pulse in the output pattern. gpio16 gpio15 gpio14 gpio13 gpio12 gpio11 gpio10 gpio9 gpio8 fan0 fan1 ntestout 02657-a-060 figure 60. nand tree test with one input stuck high a similar effect occurs if two adjacent inputs are shorted together. the example in figure 61 assumes that the current sink capability of the circuit driving the inputs is considerably higher than the source capability, so the inputs are low if either is low, but high only if both are high. when gpio12 goes high the output should go high. but because gpio12 and gpio11 are shorted, they both go high together, causing a missing pulse in the output pattern. gpio16 gpio15 gpio14 gpio13 gpio12 gpio11 gpio10 gpio9 gpio8 fan0 fan1 ntestout 02657-a-061 figure 61. nand tree test with two inputs shorted using the adm1026 when power is first applied, the adm1026 performs a power- on reset on all its registers (not eeprom), which sets them to default conditions as shown in table 12. in particular, note that all gpio pins are configured as inputs to avoid possible conflicts with circuits trying to drive these pins. the adm1026 can also be initialized at any time by writing a 1 to bit 7 of configuration register 1, which sets some registers to their default power-on conditions. this bit should be cleared by writing a 0 to it. after power-on, the adm1026 must be configured to the users specific requirements. this consists of ? writing values to the limit registers. ? configuring pins 3 to 6, and 9 to 12 as fan inputs or gpio, using configuration register 2 (address 01h). ? setting the fan divisors using the fan divisor registers (addresses 02h and 03h). ? configuring the gpio pins for input/output polarity, using gpio configuration registers 1 to 4 (addresses 08h to 0bh) and bits 6 and 7 of configuration register 3. ? setting mask bits in mask registers 1 to 6 (addresses 18h to 1dh) for any inputs that are to be masked out. ? setting up configuration registers 1 and 3, as described in table 9 and table 10. table 9. configuration register 1 bit description 0 controls the monitoring loop of the adm1026. setting bit 0 low stops the monitoring loop and puts the adm1026 into low power mode and reduces power consumption. serial bus communication is still possible with any register in the adm1026 while in low power mode. setting bit 0 high starts the monitoring loop. 1 enables or disables the int interrupt output. setting bit 1 high enables the int output, setting bit 1 low disables the output. 2 used to clear the int interrupt output when set high. gpio pins and interrupt sta tus register contents are not affected. 3 configures pins 27 and 28 as the second external temperature channel when 0, and as a in8 and a in9 when set to 1. 4 enables the therm output when set to 1. 5 enables automatic fan speed control on the dac output when set to 1. 6 enables automatic fan speed control on the pwm output when set to 1. 7 performs a soft reset when set to 1. table 10. configuration register 3 bit description 0 configures pin 42 as gpio when set to 1 or as therm when cleared to 0. 1 clears the ci latch when set to 1. thereafter, a 0 must be written to allow subsequent ci detection. 2 selects v ref as 2.5 v when set to 1 or as 1.82 v when cleared to 0. 3C5 unused. 6, 7 set up gpio16 for direction and polarity.
adm1026 rev. a | page 34 of 56 starting conversion the monitoring function (analog inputs, temperature, and fan speeds) in the adm1026 is started by writing to configuration register 1 and setting start (bit 0) high. the int _enable (bit 1) should be set to 1, and int clear (bit 2) set to 0 to enable interrupts. the therm enable bit (bit 4) should be set to 1 to enable temperature interrupts at the therm pin. apart from initially starting together, the analog measurements and fan speed measurements proceed independently, and are not synchronized in any way. reduced power mode the adm1026 can be placed in a low power mode by setting bit 0 of the configuration register to 0. this disables the internal adc. software reset function as previously mentioned, the adm1026 can be reset in software by setting bit 7 of configuration register 1 (reg. 00h) to 1. configuration register 1, 00h, should then be manually cleared. note that the software reset differs from a power-on reset in that only some of the adm1026 registers are reinitial- ized to their power-on default values. the registers that are initialized to their default values by the software reset are ? configuration registers (registers 01h to 0bh) ? mask registers 1 to 6, internal temperature offset, and status registers 4, 5, and 6 (registers 18h to 25h) ? all value registers (registers 1fh, 20h to 3fh) ? external 1 and external 2 offset registers (6eh, 6fh) note that the limit registers (0dh to 12h, 40h to 6dh) are not reset by the software reset function. this can be useful if one needs to reset the part but does not want to reprogram all parameters again. note that a power-on reset initializes all registers on the adm1026, including the limit registers. application schematic figure 62 shows how the adm1026 could be used in an application that requires system management of a pc or server. several gpios are used to read the vid codes of the cpu. up to two cpu temperature measurements can be read back. all power supply voltages are monitored in the system. up to eight fan speeds can be measured, irrespective of whether they are controlled by the adm1026 or hardwired to a system supply. the v ref output includes the recommended filtering circuitry.
adm1026 rev. a | page 35 of 56 u1 adm1026_skt 3.3v stdy sys_therm cpu1_vid4 cpu1_vid3 cpu1_vid2 cpu1_vid1 cpu1_vid0 fan x1 x3 +12v x2 x4 1 2 3 fan fan x5 q1 +12v 1 2 3 +12v 1 2 3 +12v 1 2 3 +12v 1 2 3 fan fan sdata sclock cpureset smb_alert power_good v cc 0?2.5v_out v ref _out r5 10k ? 3.3v_stby cpu1_thermdc cpu1_thermda cpu2_thermdc cpu2_thermda cpu1_v ccp cpu2_v ccp +12 v in ?12 v in +5 v in fan0/gpio0 fan1/gpio1 fan2/gpio2 fan3/gpio3 gpio15 gpio14 gpio13 gpio12 gpio11 gpio10 pwm ci int resetmain resetstby dac scl sda add agnd 3.3v stby v ref 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 16 15 14 13 fan4/gpio4 fan5/gpio5 fan6/gpio6 fan7/gpio7 dgnd gpio9 gpio8 3.3vmain a in4 a in3 a in2 a in1 a in0 therm 37 38 39 40 41 42 43 44 45 46 47 48 a in5 a in6 a in7 +v ccp +12 v in ?12v in +5 v in +v bat d2+/a in8 d2?/a in9 d1+ d1? 36 35 34 33 32 31 30 29 28 27 26 25 s1 41 c1 0.1 f b1 + r4 10k ? r3 470k ? r6 10k ? r2 2k ? r1 2k ? 02657-a-062 figure 62. adm1026 schematic
adm1026 rev. a | page 36 of 56 registers table 11. address pointer register bit name r/ w description 7C0 address pointer write address of adm1026 re gisters. see the following tables for details. table 12. list of registers hex address name power-on value description 00 configuration 1 00h configur es various operating parameters 01 configuration 2 00h configures pins 3C6 and 9C12 as fan inputs or gpio 02 fan 0C3 divisor 55h sets oscillator frequency for fan 0C3 speed measurement 03 fan 4C7 divisor 55h sets oscillator frequency for fan 4C7 speed measurement 04 dac control ffh contains value for fan speed dac (a nalog fan speed control) or minimum value for automatic fan speed control 05 pwm control ffh contains value for pwm fan speed cont rol or minimum value for automatic fan speed control 06 eeprom register 100h for factory use only 07 configuration register 300h configuration register for therm , v ref and gpio16 08 gpio config 1 00h configures gpio0 to gpio3 as input or output and as active high or active low 09 gpio config 2 00h configures gpio4 to gpio7 as input or output and as active high or active low 0a gpio config 3 00h configures gpio8 to gpio11 as input or output and as active high or active low 0b gpio config 4 00h configures gpio12 to gpio15 as input or output and as active high or active low 0c eeprom register 2 00h for factory use only 0d int temp therm limit 37h (55c) high limit for therm interrupt output based on internal temperature measurement 0e tdm1 therm limit 50h (80c) high limit for therm interrupt output based on remote channel 1 (d1) temperature measurement 0f tdm2 therm limit 50h (80c) high limit for therm interrupt output based on remote channel 2 (d2) temperature measurement 10 int temp t min 28h (40c) t min value for automatic fan speed cont rol based on internal temperature measurement 11 tdm1 t min 40h (64c) t min value for automatic fan speed control based on remote channel 1 (d1) temperature measurement 12 tdm2 t min 40h (64c) t min value for automatic fan speed control based on remote channel 2 (d2) temperature measurement 13 eeprom register 3 00h configures eeprom for read/write/erase, etc. 14 test register 1 00h manufacturers test register 15 test register 2 00h for manufacturers use only 16 manufacturers id 41h cont ains manufacturers id code 17 revision 4xh contains code for major and minor revisions 18 mask register 1 00h interrupt mask regi ster for temperature and supply voltage faults 19 mask register 2 00h interrupt ma sk register for analog input faults 1a mask register 3 00h interru pt mask register for fan faults 1b mask register 4 00h interrupt mask register for local temp, v bat , a in8 , therm , afc, ci and gpio16 1c mask register 5 00h interrupt mask register for gpio0 to gpio7 1d mask register 6 00h interrupt mask register for gpio8 to gpio15 1e int temp offset 00h offset regist er for internal temperature measurement 1f int temp value 00h measured temperature from onCchip sensor 20 status register 1 00h interrupt status regi ster for external temp an d supply voltage faults 21 status register 2 00h interrupt st atus register for an alog input faults 22 status register 3 00h interrupt status register for fan faults 23 status register 4 00h interrupt status register for local temp, v bat , a in8 , therm , afc, ci, and gpio16
adm1026 rev. a | page 37 of 56 hex address name power-on value description 24 status register 5 00h interrupt status register for gpio0 to gpio7 25 status register 6 00h interrupt status register for gpio8 to gpio15 26 v bat value 00h measured value of v bat 27 a in8 value 00h measured value of a in8 28 tdm1 value 00h measured value of remote temperature channel 1 (d1) 29 tdm2/a in9 value 00h measured value of remo te temperature channel 2 (d2) or a in9 2a 3.3 v stby value 00h measured value of 3.3 v stby 2b 3.3 v main value 00h measured value of 3.3 v main 2c +5 v value 00h measured value of +5 v supply 2d v ccp value 00h measured value of processor core voltage 2e +12 v value 00h measured value of +12 v supply 2f ? 12 v value 00h measured value of ? 12 v supply 30 a in0 value 00h measured value of a in0 31 a in1 value 00h measured value of a in1 32 a in2 value 00h measured value of a in2 33 a in3 value 00h measured value of a in3 34 a in4 value 00h measured value of a in4 35 a in5 value 00h measured value of a in5 36 a in6 value 00h measured value of a in6 37 a in7 value 00h measured value of a in7 38 fan0 value 00h measured speed of fan 0 39 fan1 value 00h measured speed of fan 1 3a fan2 value 00h measured speed of fan 2 3b fan3 value 00h measured speed of fan 3 3c fan4 value 00h measured speed of fan 4 3d fan5 value 00h measured speed of fan 5 3e fan6 value 00h measured speed of fan 6 3f fan7 value 00h measured speed of fan 7 40 tdm1 high limit 64h (100c) high limit fo r remote temperature channel 1 (d1) measurement 41 tdm2/a in9 high limit 64h (100c) high limit fo r remote temperature channel 2 (d2) or a in9 measurement 42 3.3 v stby high limit ffh high limit for 3.3 v stby measurement 43 3.3 v main high limit ffh high limit for 3.3 v main measurement 44 +5 v high limit ffh high limit for +5 v supply measurement 45 v ccp high limit ffh high limit for processor core voltage measurement 46 +12 v high limit ffh high limit for +12 v supply measurement 47 ? 12 v high limit ffh high limit for ? 12 v supply measurement 48 tdm1 low limit 80h low limit for remo te temperature channel 1 (d1) measurement 49 tdm2/a in9 low limit 80h low limit for remo te temperature channel 2 (d2) or a in9 measurement 4a 3.3 v stby low limit 00h lo w limit for 3.3 v stby measurement 4b 3.3 v main low limit 00h lo w limit for 3.3 v main measurement 4c +5 v low limit 00h low limit for +5 v supply 4d v ccp low limit 00h low limit for pr ocessor core voltage measurement 4e +12 v low limit 00h low limit for +12 v supply measurement 4f ? 12 v low limit 00h low limit for ? 12 v supply measurement 50 a in0 high limit ffh high limit for a in0 measurement 51 a in1 high limit ffh high limit for a in1 measurement 52 a in2 high limit ffh high limit for a in2 measurement 53 a in3 high limit ffh high limit for a in3 measurement 54 a in4 high limit ffh high limit for a in4 measurement 55 a in5 high limit ffh high limit for a in5 measurement 56 a in6 high limit ffh high limit for a in6 measurement 57 a in7 high limit ffh high limit for a in7 measurement
adm1026 rev. a | page 38 of 56 hex address name power-on value description 58 a in0 low limit 00h low limit for a in0 measurement 59 a in1 low limit 00h low limit for a in1 measurement 5a a in2 low limit 00h low limit for a in2 measurement 5b a in3 low limit 00h low limit for a in3 measurement 5c a in4 low limit 00h low limit for a in4 measurement 5d a in5 low limit 00h low limit for a in5 measurement 5e a in6 low limit 00h low limit for a in6 measurement 5f a in7 low limit 00h low limit for a in7 measurement 60 fan0 high limit ffh high limit fo r fan 0 speed measurement (no low limit) 61 fan1 high limit ffh high limit fo r fan 1 speed measurement (no low limit) 62 fan2 high limit ffh high limit fo r fan 2 speed measurement (no low limit) 63 fan3 high limit ffh high limit fo r fan 3 speed measurement (no low limit) 64 fan4 high limit ffh high limit fo r fan 4 speed measurement (no low limit) 65 fan5 high limit ffh high limit fo r fan 5 speed measurement (no low limit) 66 fan6 high limit ffh high limit fo r fan 6 speed measurement (no low limit) 67 fan7 high limit ffh high limit fo r fan 7 speed measurement (no low limit) 68 int. temp. high limit 50h (80c) hi gh limit for local temperature measurement 69 int. temp. low limit 80h low l imit for local temperature measurement 6a v bat high limit ffh high limit for v bat measurement 6b v bat low limit 00h low limit for v bat measurement 6c a in8 high limit ffh high limit for a in8 measurement 6d a in8 low limit 00h low limit for a in8 measurement 6e ext1 temp offset 00h offset re gister for remote temperature channel 1 6f ext2 temp offset 00h offset re gister for remote temperature channel 2 detailed register descriptions table 13. register 00h, configuration register 1 (power-on default 00h) bit name r/ w description 0 monitor = 0 r/w when this bit is set the adm1026 monitors al l voltage, temperature and fan channels in a round robin manner. 1 int enable = 0 r/w when this bit is set, the int output pin is enabled. 2 int clear = 0 r/w setting this bit clears an in terrupt from the voltage, temperature or fan speed channels. because gpio interrupts are level triggered, this bit has no effect on interrupts originating from gpio channels. this bit is cleared by writing a 0 to it. if in monitoring mode vo ltages, temperatures and fan speeds continue to be monitored after writing to this bit to clear an in terrupt, so an interrupt may be set again on the next monitoring cycle. 3 enable voltage/ext2 = 0 r/w when this bit is 1, th e adm1026 monitors voltage (a in8 and a in9 ) on pins 28 and 27, respectively. when this bit is 0, the adm1026 monitors a se cond thermal diode temperature channel, d2, on these pins. if the second thermal diode channel is not being used, it is recommended that the bit be set to 1. 4 enable therm = 0 r/w when this bit is 1, the therm pin (pin 42) is asserted (go low) if any of the therm limits are exceeded. if therm is pulled low as an input, the dac and pwm outputs are forced to full scale until therm is taken high. 5 enable dac afc = 0 r/w when this bit is 1, the dac output is enab led for automatic fan speed control (afc) based on temperature. when this bit is 0, the dac output reflects the value in reg 04h, the dac control register. 6 enable pwm afc = 0 r/w when this bit is 1, the pwm output is enable d for automatic fan speed control (afc) based on temperature. when this bit is 0, the pwm output reflects the value in reg 05h, the pwm control register. 7 software reset = 0 r/w writing a 1 to this bit restores all registers to the power-on defaults. this bi t is cleared by writing a 0 to it. for more info, see the so ftware reset function section.
adm1026 rev. a | page 39 of 56 table 14. register 01h, configuration register 2 (power-on default 00h) bit name r/ w description 0 enable gpio0/fan0 = 0 r/w when this bit is 1, pin 3 is enabled as a general- purpose i/o pin (gpio0), otherwise it is a fan tach measurement input (fan 0). 1 enable gpio1/fan1 = 0 r/w when this bit is 1, pin 4 is enabled as a general- purpose i/o pin (gpio1), otherwise it is a fan tach measurement input (fan 1). 2 enable gpio2/fan2 = 0 r/w when this bit is 1, pin 5 is enabled as a general- purpose i/o pin (gpio2), otherwise it is a fan tach measurement input (fan 2). 3 enable gpio3/fan3 = 0 r/w when this bit is 1, pin 6 is enabled as a general- purpose i/o pin (gpio3), otherwise it is a fan tach measurement input (fan 3). 4 enable gpio4/fan4 = 0 r/w when this bit is 1, pin 9 is enabled as a general- purpose i/o pin (gpio4), otherwise it is a fan tach measurement input (fan 4). 5 enable gpio5/fan5 = 0 r/w when this bit is 1, pin 10 is enabled as a general- purpose i/o pin (gpio5), otherwise it is a fan tach measurement input (fan 5). 6 enable gpio6/fan6 = 0 r/w when this bit is 1, pin 11 is enabled as a general- purpose i/o pin (gpio6), otherwise it is a fan tach measurement input (fan 6). 7 enable gpio7/fan7 = 0 r/w when this bit is 1, pin 12 is enabled as a general- purpose i/o pin (gpio7), otherwise it is a fan tach measurement input (fan 7). table 15. register 02h, fans 0 to 3 fan divisor register (power-on default 55h) bit name r/ w description 1C0 fan 0 divisor r/w sets the oscillator prescaler division ratio for fa n 0 speed measurement. the division ratios, oscillator frequencies, and typical fan speeds (based on 2 tach pulses per revolution) are as follows: code divide by oscillator frequency (khz) fan speed (rpm) 00 1 22.5 8800, nominal, for count of 153 01 2 11.25 4400, nominal, for count of 153 10 4 5.62 2200, nominal, for count of 153 11 8 2.81 1100, nominal, for count of 153 3C2 fan 1 divisor r/w same as fan 0 5C4 fan 2 divisor r/w same as fan 0 7C6 fan 3 divisor r/w same as fan 0 table 16. register 03h, fans 4 to 7 fan divisor register (power-on default 55h) bit name r/ w description 1C0 fan 4 divisor r/w sets the oscillator prescaler division ratio for fa n 4 speed measurement. the division ratios, oscillator frequencies, and typical fan speeds (based on 2 tach pulses per revolution) are as follows: code divide by oscillator frequency (khz) fan speed (rpm) 00 1 22.5 8800, nominal, for count of 153 01 2 11.25 4400, nominal, for count of 153 10 4 5.62 2200, nominal, for count of 153 11 8 2.81 1100, nominal, for count of 153 3-2 fan 5 divisor r/w same as fan 4 5-4 fan 6 divisor r/w same as fan 4 7-6 fan 7 divisor r/w same as fan 4 table 17. register 04h, dac control register (power-on default ffh) bit name r/ w description 7C0 dac control r/w this register contains the value to which the fa n speed dac is programmed in normal mode, or the 4 msbs contain the minimum fan speed in auto fan speed control mode.
adm1026 rev. a | page 40 of 56 table 18. register 05h, pwm control register (power-on default ffh) bit name r/ w description 7C4 pwm control r/w this register contains the value to whic h the pwm fan speed is programmed in normal mode, or the 4 msbs contain the minimum fa n speed in auto fan speed control mode. 0000 = 0% duty cycle 0001 = 7% duty cycle 0101 = 33% duty cycle 0110 = 40% duty cycle 0111 = 47% duty cycle 1110 = 93% duty cycle 1111 = 100% duty cycle 3C0 unused r undefined table 19. register 06h, eeprom register 1 (power-on default 00h) bit name r/ w description 7C0 factory use r/w for factory use only. do not write to this register. table 20. register 07h, configuration register 3 (power-on default 00h) bit name r/ w description 0 enable gpio16/ therm = 0 r/w when this bit is 1, pin 42 is enabled as a general-purpose i/o pin (gpio16); otherwise it is the therm output. 1 ci clear = 0 r/w writing a 1 to this bit clears the ci latch. this bit is cl eared by writing a 0 to it. 2 v ref select = 0 r/w when this bit is 0, v ref (pin 24) outputs 1.82 v, othe rwise, it outputs 2.5 v. 5C3 unused r undefined, reads back 0. 6 gpio16 direction r/w when this bit is 0, gpio16 is configured as an input; otherwise, it is an output. 7 gpio16 polarity r/w when this bit is 0, gpio16 is active low; otherwise, it is active high. table 21. register 08h, gpio configuration register 1 (power-on default 00h) bit name r/ w description 0 gpio0 direction r/w when this bit is 0, gpio0 is configured as an input; otherwise, it is an output. 1 gpio0 polarity r/w when this bit is 0, gpio0 is active low; otherwise it is active high. 2 gpio1 direction r/w when this bit is 0, gpio1 is configured as an input; otherwise, it is an output. 3 gpio1 polarity r/w when this bit is 0, gpio1 is active low; otherwise it is active high. 4 gpio2 direction r/w when this bit is 0, gpio2 is configured as an input; otherwise, it is an output. 5 gpio2 polarity r/w when this bit is 0, gpio2 is active low; otherwise, it is active high. 6 gpio3 direction r/w when this bit is 0, gpio3 is configured as an input; otherwise, it is an output. 7 gpio3 polarity r/w when this bit is 0, gpio3 is active low; otherwise, it is active high. table 22. register 09h, gpio configuration register 2 (power-on default 00h) bit name r/ w description 0 gpio4 direction r/w when this bit is 0, gpio4 is configured as an input; otherwise, it is an output. 1 gpio4 polarity r/w when this bit is 0, gpio4 is active low; otherwise, it is active high. 2 gpio5 direction r/w when this bit is 0, gpio5 is configured as an input; otherwise, it is an output. 3 gpio5 polarity r/w when this bit is 0, gpio5 is active low; otherwise, it is active high. 4 gpio6 direction r/w when this bit is 0, gpio6 is configured as an input; otherwise, it is an output. 5 gpio6 polarity r/w when this bit is 0, gpio6 is active low; otherwise, it is active high. 6 gpio7 direction r/w when this bit is 0, gpio7 is configured as an input; otherwise, it is an output. 7 gpio7 polarity r/w when this bit is 0, gpio7 is active low; otherwise, it is active high.
adm1026 rev. a | page 41 of 56 table 23. register 0ah, gpio configuration register 3 (power-on default 00h) bit name r/ w description 0 gpio8 direction r/w when this bit is 0, gpio8 is configured as an input; otherwise, it is an output. 1 gpio8 polarity r/w when this bit is 0, gpio8 is active low; otherwise, it is active high. 2 gpio9 direction r/w when this bit is 0, gpio9 is configured as an input; otherwise, it is an output. 3 gpio9 polarity r/w when this bit is 0, gpio9 is active low; otherwise, it is active high. 4 gpio10 direction r/w when this bit is 0, gpio10 is configured as an input; otherwise, it is an output. 5 gpio10 polarity r/w when this bit is 0, gpio10 is active low; otherwise, it is active high. 6 gpio11 direction r/w when this bit is 0, gpio11 is configured as an input; otherwise, it is an output. 7 gpio11 polarity r/w when this bit is 0, gpio11 is active low; otherwise, it is active high. table 24. register 0bh, gpio configuration register 4 (power-on default 00h) bit name r/ w description 0 gpio12 direction r/w when this bit is 0, gpio12 is configured as an input; otherwise, it is an output. 1 gpio12 polarity r/w when this bit is 0, gpio12 is active low; otherwise, it is active high. 2 gpio13 direction r/w when this bit is 0, gpio13 is configured as an input; otherwise, it is an output. 3 gpio13 polarity r/w when this bit is 0, gpio13 is active low; otherwise, it is active high. 4 gpio14 direction r/w when this bit is 0, gpio14 is configured as an input; otherwise, it is an output. 5 gpio14 polarity r/w when this bit is 0, gpio14 is active low; otherwise, it is active high. 6 gpio15 direction r/w when this bit is 0, gpio15 is configured as an input; otherwise, it is an output. 7 gpio15 polarity r/w when this bit is 0, gpio15 is active low; otherwise, it is active high. table 25. register 0ch, eeprom register 2 (power-on default 00h) bit name r/ w description 7C0 factory use r for factory use on ly. do not write to this register. table 26. register 0dh, internal temperature therm limit (power-on default, 37h 55c) bit name r/ w description 7C0 int temp therm limit r/w this register contains the therm limit for the internal temperatur e channel. exceeding this limit causes the therm output pin to be asserted. table 27. register 0eh, tdm1 therm limit (power-on default 50h, 80c) bit name r/ w description 7C0 tdm1 therm limit r/w this register contains the therm limit for the tdm1 temperature channel. exceeding this limit causes the therm output pin to be asserted. table 28. register 0fh, tdm2 therm limit (power-on default 50h, 80c) bit name r/ w description 7C0 tdm2 therm limit r/w this register contains the therm limit for the tdm2 temperature channel. exceeding this limit causes the therm output pin to be asserted. table 29. register 10h, internal temperature t min (power-on default 28h, 40c) bit name r/ w description 7C0 internal temp t min r/w this register contains the t min value for automatic fan speed control based on the internal temperature channel. table 30. register 11h, tdm1 temperature t min (power-on default 40h, 64c) bit name r/ w description 7C0 tdm1 temp t min r/w this register contains the t min value for automatic fan speed control based on the tdm1 temperature channel.
adm1026 rev. a | page 42 of 56 table 31. register 12h, tdm2 temperature t min (power-on default 40h, 64c) bit name r/ w description 7C0 tdm2 temp t min r/w this register contains the t min value for automatic fan speed cont rol based on the tdm2 temperature channel. table 32. register 13h, eeprom register 3 (power-on default 00h) bit name r/ w description 0 read r/w setting this bit puts the eeprom into read mode. 1 write r/w setting this bit puts the eeprom in write (program) mode. 2 erase r/w setting this bit puts the eeprom into erase mode. 3 write protect r/w once setting this bit protects the eeprom against accidental writing or erasure. this bit is write-once and can only be cleared by a power-on reset. 4 test mode bit 0 r/w test mode bits. for factory use only 5 test mode bit 1 r/w test mode bits. for factory use only. 6 test mode bit 2 r/w test mode bits. for factory use only 7 clock extend r/w setting this bit enables smbus clock extension. the adm1026 can pull scl low to extend the clock pulse if it cannot accept any more data. it is reco mmended to set this bit to 1 to extend the clock pulse during repeated eeprom wr ite or block write operations. table 33. register 14h, manufacturers test register 1 (power-on default 00h) bit name r/ w description 7C0 manufacturers test 1 r/w this register is used by the ma nufacturer for test purposes. it sh ould not be read from or written to in normal operation. table 34. register 15h, manufacturers test register 2 (power-on default 00h) bit name r/ w description 7C0 manufacturers test 2 r/w this register is used by the ma nufacturer for test purposes. it sh ould not be read from or written to in normal operation. table 35. register 16h, manufacturers id (power-on default 41h) bit name r/ w description 7C0 manufacturers id code r this register contains the manufacturers id code. table 36. register 17h, revision register (power-on default 4xh) bit name r/ w description 3C0 minor revision code r this nibble contains the manufacturers code for minor revisions to the device. rev 1 = 0h, rev 2 = 1h, and so on. 7C4 major revision code r this nibble denotes the gene ration of the device. for the adm1026, this nibble reads 4h. table 37. register 18h, mask register 1 (power-on default 00h) bit name r/ w description 0 ext1 temp mask = 0 r/w when this bit is set, in terrupts generated on the ext1 temperature channel are masked out. 1 ext2 temp r/w when this bit is set, in terrupts generated on the ext2/a in9 channel are masked out. 2 3.3 v stby mask = 0 r/w when this bit is set, in terrupts generated on the 3.3 v stby voltage channel are masked out. 3 3.3 v main mask = 0 r/w when this bit is set, in terrupts generated on the 3.3 v main voltage channel are masked out. 4 +5 v mask = 0 r/w when this bit is set, in terrupts generated on the +5 v voltage channel are masked out. 5 v ccp mask = 0 r/w when this bit is set, in terrupts generated on the v ccp voltage channel are masked out. 6 +12 v mask = 0 r/w when this bit is set, in terrupts generated on the +12 v voltage channel are masked out. 7 ?12 v mask = 0 r/w when this bit is set, in terrupts generated on the ?12 v voltage channel are masked out.
adm1026 rev. a | page 43 of 56 table 38. register 19h, mask register 2 (power-on default 00h) bit name r/ w description 0 a in0 mask = 0 r/w when this bit is set, in terrupts generated on the a in0 voltage channel are masked out. 1 a in1 mask = 0 r/w when this bit is set, in terrupts generated on the a in1 voltage channel are masked out. 2 a in2 mask = 0 r/w when this bit is set, in terrupts generated on the a in2 voltage channel are masked out. 3 a in3 mask = 0 r/w when this bit is set, in terrupts generated on the a in3 voltage channel are masked out. 4 a in4 mask = 0 r/w when this bit is set, in terrupts generated on the a in4 voltage channel are masked out. 5 a in5 mask = 0 r/w when this bit is set, in terrupts generated on the a in5 voltage channel are masked out. 6 a in6 mask = 0 r/w when this bit is set, in terrupts generated on the a in6 voltage channel are masked out. 7 a in7 mask = 0 r/w when this bit is set, in terrupts generated on the a in7 voltage channel are masked out. table 39. register 1ah, mask register 3 (power-on default 00h) bit name r/ w description 0 fan0 mask = 0 r/w when this bit is set, in terrupts generated on the fan0 tach channel are masked out. 1 fan1 mask = 0 r/w when this bit is set, in terrupts generated on the fan1 tach channel are masked out. 2 fan2 mask = 0 r/w when this bit is set, in terrupts generated on the fan2 tach channel are masked out. 3 fan3 mask = 0 r/w when this bit is set, in terrupts generated on the fan3 tach channel are masked out. 4 fan4 mask = 0 r/w when this bit is set, in terrupts generated on the fan4 tach channel are masked out. 5 fan5 mask = 0 r/w when this bit is set, in terrupts generated on the fan5 tach channel are masked out. 6 fan6 mask = 0 r/w when this bit is set, in terrupts generated on the fan6 tach channel are masked out. 7 fan7 mask = 0 r/w when this bit is set, in terrupts generated on the fan7 tach channel are masked out. table 40. register 1bh, mask register 4 (power-on default 00h) bit name r/ w description 0 int temp mask = 0 r/w when this bit is set, interrupts generated on th e internal temperature channel are masked out. 1 v bat mask = 0 r/w when this bit is set, interrupts generated on the v bat voltage channel are masked out. 2 a in8 mask = 0 r/w when this bit is set, interrupts generated on the a in8 voltage channel are masked out. 3 therm mask = 0 r/w when this bit is set, interrupts generated from therm events are masked out. 4 afc mask = 0 r/w when this bit is set, interrupts generated from automatic fan control events are masked out. 5 unused r/w unused. reads back 0. 6 ci mask = 0 r/w when this bit is set, interrupts generated by the chassis intrusion input are masked out. 7 gpio16 mask = 0 r/w when this bit is set, interrupts generate d on the gpio16 channel are masked out. table 41. register 1ch, mask register 5 (power-on default 00h) bit name r/ w description 0 gpio0 mask = 0 r/w when this bit is set, in terrupts generated on the gpio0 channel are masked out. 1 gpio1 mask = 0 r/w when this bit is set, in terrupts generated on the gpio1 channel are masked out. 2 gpio2 mask = 0 r/w when this bit is set, in terrupts generated on the gpio2 channel are masked out. 3 gpio3 mask = 0 r/w when this bit is set, in terrupts generated on the gpio3 channel are masked out. 4 gpio4 mask = 0 r/w when this bit is set, in terrupts generated on the gpio4 channel are masked out. 5 gpio5 mask = 0 r/w when this bit is set, in terrupts generated on the gpio5 channel are masked out. 6 gpio6 mask = 0 r/w when this bit is set, in terrupts generated on the gpio6 channel are masked out. 7 gpio7 mask = 0 r/w when this bit is set, in terrupts generated on the gpio7 channel are masked out.
adm1026 rev. a | page 44 of 56 table 42. register 1dh, mask register 6 (power-on default 00h) bit name r/ w description 0 gpio8 mask = 0 r/w when this bit is set, in terrupts generated on the gpio8 channel are masked out. 1 gpio9 mask = 0 r/w when this bit is set, in terrupts generated on the gpio9 channel are masked out. 2 gpio10 mask = 0 r/w when this bit is set, in terrupts generated on the gpio10 channel are masked out. 3 gpio11mask = 0 r/w when this bit is set, in terrupts generated on the gpio11 channel are masked out. 4 gpio12 mask = 0 r/w when this bit is set, in terrupts generated on the gpio12 channel are masked out. 5 gpio13 mask = 0 r/w when this bit is set, in terrupts generated on the gpio13 channel are masked out. 6 gpio14 mask = 0 r/w when this bit is set, in terrupts generated on the gpio14 channel are masked out. 7 gpio15 mask = 0 r/w when this bit is set, in terrupts generated on the gpio15 channel are masked out. table 43. register 1eh, int temp offset (power-on default 00h) bit name r/ w description 7C0 int temp offset r/w this register contains the offset value for th e internal temperature cha nnel, a twos complement result before it is stored or compared to limits. in this way, a sort of one-point calibration can be done whereby the whole transfer function of the channel can be moved up or down. from a software point of view, this may be a very simp le method to vary the characteristics of the measurement channel if the thermal characteristics change for any reason (for instance from one chassis to another), if the measurement point is mo ved, if a plug-in card is inserted or removed, and so on. table 44. register 1fh, int temp measured value (power-on default 00h) bit name r/ w description 7C0 int temp value r this register contains the measured value of the internal temperature channel. table 45. register 20h, status register 1 (power-on default 00h) bit name r/ w description 0 ext1 temp status = 0 r 1, if ext1 value is above the high limit or belo w the low limit on the previous conversion cycle; 0 otherwise. this bit is set (once only) if a therm mode is engaged as a resu lt of ext1 temp readings exceeding the ext1 therm limit. this bit is also set (once only) if therm mode is disengaged as a result of ext1 temperature read ings going 5c below ext1 therm limit. 1 ext2 temp status = 0 r 1, if ext 2 value (or a in9 if in voltage measurement mode) is above the /a in9 status = 0 high limit or below the low limit on the previous conversion cycle; 0 otherwise. this bit is set (once only) if a therm mode is engaged as a result of ext2 te mperature readings exceeding the ext2 therm limit. this bit is also set (once only) if therm mode is disengaged as a result of ext2 temperature readings going 5c below ext2 therm limit. 2 3.3 v stby status = 0 r 1, if 3.3 v stby value is above the high limit or below the low limit on the previous conversion cycle; 0 otherwise. 3 3.3 v main status = 0 r 1, if 3.3 v main value is above the high limit or below the low limit on the previous conversion cycle; 0 otherwise. 4 +5 v status = 0 r 1, if +5 v value is above the high limit or belo w the low limit on the previous conversion cycle; 0 otherwise. 5 v ccp status = 0 r 1, if v ccp value is above the high limit or below the low limit on the previous conversion cycle; 0 otherwise. 6 +12 v status = 0 r 1, if +12 v value is above the high limit or belo w the low limit on the previous conversion cycle; 0 otherwise. 7 ?12 v status = 0 r 1, if ? 12 v value is above the high limit or below the low limit on the previous conversion cycle; 0 otherwise.
adm1026 rev. a | page 45 of 56 table 46. register 21h, status register 2 (power-on default 00h) bit name r/ w description 0 a in0 status = 0 r 1, if a in0 to a in7 value is above the high limit or below the low limit on the previous conversion cycle;0 otherwise. 1 a in1 status = 0 r 1, if a in0 to a in7 value is above the high limit or below the low limit on the previous conversion cycle;0 otherwise. 2 a in2 status = 0 r 1, if a in0 to a in7 value is above the high limit or below the low limit on the previous conversion cycle;0 otherwise. 3 a in3 status = 0 r 1, if a in0 to a in7 value is above the high limit or below the low limit on the previous conversion cycle;0 otherwise. 4 a in4 status = 0 r 1, if a in0 to a in7 value is above the high limit or below the low limit on the previous conversion cycle;0 otherwise. 5 a in5 status = 0 r 1, if a in0 to a in7 value is above the high limit or below the low limit on the previous conversion cycle;0 otherwise. 6 a in6 status = 0 r 1, if a in0 to a in7 value is above the high limit or below the low limit on the previous conversion cycle;0 otherwise. 7 a in7 status = 0 r 1, if a in0 to a in7 value is above the high limit or below the low limit on the previous conversion cycle;0 otherwise. table 47. register 22h, status register 3 (power-on default 00h) bit name r/ w description 0 fan0 status 1 = 0 r 1, if fan0 to fan7 value is above the high limit on the previous conversion cycle; 0 otherwise. 1 fan1 status 1 = 0 r 1, if fan0 to fan7 value is abov e the high limit on the previous conversion cycle; 0 otherwise. 2 fan2 status 1 = 0 r 1, if fan0 to fan7 value is abov e the high limit on the previous conversion cycle; 0 otherwise. 3 fan3 status 1 = 0 r 1, if fan0 to fan7 value is abov e the high limit on the previous conversion cycle; 0 otherwise. 4 fan4 status 1 = 0 r 1, if fan0 to fan7 value is abov e the high limit on the previous conversion cycle; 0 otherwise. 5 fan5 status 1 = 0 r 1, if fan0 to fan7 value is abov e the high limit on the previous conversion cycle; 0 otherwise. 6 fan6 status 1 = 0 r 1, if fan0 to fan7 value is abov e the high limit on the previous conversion cycle; 0 otherwise. 7 fan7 status 1 = 0 r 1, if fan0 to fan7 value is abov e the high limit on the previous conversion cycle; 0 otherwise. table 48. register 23h, status register 4 (power-on default 00h) bit name r/ w description 0 int temp status = 0 r 1, if int value is above the high limit or below the low limit on the previous conversion cycle, 0 otherwise. this bit is se t (once only) if a therm mode is engaged as a result of int temperature readings exceeding the int therm limit. this bit is also set (once only) if therm mode is disengaged as a result of internal temperatur e readings going 5c below int therm limit. 1 v bat status = 0 r 1, if v bat value is above the high limit or below the low limit on the previous conversion cycle, 0 otherwise. 2 a in8 status = 0 r 1, if a in8 value is above the high limit or below the low limit on the previous conversion cycle, 0 otherwise. 3 therm status = 0 r this bit is set (once only) if a therm mode is engaged as a resu lt of temperature readings exceeding the therm limits on any channel. this bit is also set (once only) if therm mode is disengaged as a result of temperature readings going 5c below therm limits on any channel. 4 afc status = 0 r this bit is set (once only) if the fan turns on wh en in automatic fan speed control (afc) mode as a result of a temperature reading exceeding t min on any channel. this bit is also set (once only) if the fan turns off when in automa tic fan speed control mode. 5 unused r unused. reads back 0. 6 ci status = 0 r this bit latches a chassis intrusion event. 7 gpio16 status = 0 r when gpio16 is configured as an input, this bit is set when gpio 16 is asserted. (asserted may be active high or active low depending on the setting in gpio configuration register.) r/w when gpio16 is configured as an output, setting this bit assert s gpio16. (asserted may be active high or active low depending on setting in gpio configuration register.)
adm1026 rev. a | page 46 of 56 table 49. register 24h, status register 5 (power-on default 00h) bit name r/ w 1 description 0 gpio0 status = 0 r when gpio0 is configured as an input, this bit is set when gpio 0 is asserted. (asserted may be active high or active low depending on setting of bit 1 in gpio configuration register 1.) r/w when gpio0 is configured as an output, setting this bit asserts gp io0. (asserted may be active high or active low depending on setting of bi t 1 in gpio configuration register 1.) 1 gpio1 status = 0 r when gpio1 is configured as an input, this bit is set when gpio 1 is asserted. (asserted may be active high or active low depending on setting of bit 3 in gpio configuration register 1.) r/w when gpio1 is configured as an output, setting this bit asserts gp io1. (asserted may be active high or active low depending on setting of bi t 3 in gpio configuration register 1.) 2 gpio2 status = 0 r when gpio2 is configured as an input, this bit is set when gpio 2 is asserted. (asserted may be active high or active low depending on setting of bit 5 in gpio configuration register 1.) r/w when gpio2 is configured as an output, setting this bit asserts gpio 2. (asserted may be active high or active low depending on setting of bi t 5 in gpio configuration register 1.) 3 gpio3 status = 0 r when gpio3 is configured as an input, this bit is set when gpio 3 is asserted. (asserted may be active high or active low depending on setting of bit 7 in gpio configuration register 1.) r/w when gpio3 is configured as an output, setting this bit asserts gp io3. (asserted may be active high or active low depending on setting of bi t 7 in gpio configuration register 1.) 4 gpio4 status = 0 r when gpio4 is configured as an input, this bit is set when gpio 4 is asserted. (asserted may be active high or active low depending on setting of bit 1 in gpio configuration register 2.) r/w when gpio4 is configured as an output, setting this bit asserts gp io4. (asserted may be active high or active low depending on setting of bi t 1 in gpio configuration register 2.) 5 gpio5 status = 0 r when gpio5 is configured as an input, this bit is set when gpio 5 is asserted. (asserted may be active high or active low depending on setting of bit 3 in gpio configuration register 2.) r/w when gpio5 is configured as an output, setting this bit asserts gp io5. (asserted may be active high or active low depending on setting of bi t 3 in gpio configuration register 2.) 6 gpio6 status = 0 r when gpio6 is configured as an input, this bit is set when gpio 6 is asserted. (asserted may be active high or active low depending on setting of bit 5 in gpio configuration register 2.) r/w when gpio6 is configured as an output, setting this bit asserts gp io6. (asserted may be active high or active low depending on setting of bi t 5 in gpio configuration register 2.) 7 gpio7 status = 0 r when gpio7 is configured as an input, this bit is set when gpio 7 is asserted. (asserted may be active high or active low depending on setting of bit 7 in gpio configuration register 2.) r/w when gpio7 is configured as an output, setting this bit asserts gp io7. (asserted may be active high or active low depending on setting of bi t 7 in gpio configuration register 2.) 1 gpio status bits can be written only when a gpio pin is configure d as output. read-only otherwise.
adm1026 rev. a | page 47 of 56 table 50. register 25h, status register 6 (power-on default 00h) bit name r/ w 1 description 0 gpio8 status = 0 r when gpio8 is configured as an in put, this bit is set wh en gpio8 is asserted. (asserted may be active high or active low depending on setting of bit 1 in gpio configuration register 3.) r/w when gpio8 is configured as an o utput, setting this bit asserts gpio8. (asserted may be active high or active low depending on setting of bit 1 in gpio configuration register 3.) 1 gpio9 status = 0 r when gpio9 is configured as an in put, this bit is set wh en gpio9 is asserted. (asserted may be active high or active low depending on setting of bit 3 in gpio configuration register 3.) r/w when gpio9 is configured as an o utput, setting this bit asserts gpio9. (asserted may be active high or active low depending on setting of bit 3 in gpio configuration register 3.) 2 gpio10 status = 0 r when gpio10 is configured as an input, this bit is set when gpio 10 is asserted. (asserted may be active high or active low depending on setting of bit 5 in gpio configuration register 3.) r/w when gpio10 is configured as an output, setting this bit asserts gp io10. (asserted may be active high or active low depending on setting of bi t 5 in gpio configuration register 3.) 3 gpio11 status = 0 r when gpio11 is configured as an input, this bit is set when gpio 11 is asserted. (asserted may be active high or active low depending on setting of bit 7 in gpio configuration register 3.) r/w when gpio11 is configured as an output, setting this bit asserts gp io11. (asserted may be active high or active low depending on setting of bi t 7 in gpio configuration register 3.) 4 gpio12 status = 0 r when gpio12 is configured as an input, this bit is set when gpio 12 is asserted. (asserted may be active high or active low depending on setting of bit 1 in gpio configuration register 4.) r/w when gpio12 is configured as an output, setting this bit asserts gp io12. (asserted may be active high or active low depending on setting of bi t 1 in gpio configuration register 4.) 5 gpio13 status = 0 r when gpio13 is configured as an input , this bit is set when gpio 13 is asserted. (asserted may be active high or active low depending on setting of bit 3 in gpio configuration register 4.) r/w when gpio13 is configured as an output, setting this bit asserts gp io13. (asserted may be active high or active low depending on setting of bi t 3 in gpio configuration register 4.) 6 gpio14 status = 0 r when gpio14 is configured as an input , this bit is set when gpio 14 is asserted. (asserted may be active high or active low depending on setting of bit 5 in gpio configuration register 4.) r/w when gpio14 is configured as an output, setting this bit asserts gp io14. (asserted may be active high or active low depending on setting of bi t 5 in gpio configuration register 4.) 7 gpio15 status = 0 r when gpio15 is configured as an input, this bit is set when gpio 15 is asserted. (asserted may be active high or active low depending on setting of bit 7 in gpio configuration register 4.) r/w when gpio15 is configured as an output, setting this bit asserts gp io15. (asserted may be active high or active low depending on setting of bi t 7 in gpio configuration register 4.) 1 gpio status bits can be written only when a gpio pin is configure d as output. read-only otherwise. table 51. register 26h, v bat measured value (power-on default 00h) bit name r/ w description 7C0 v bat value r this register contains the measured value of the v bat analog input channel. table 52. register 27h, a in8 measured value (power-on default 00h) bit name r/ w description 7C0 a in8 value r this register contains the measured value of the a in8 analog input channel. table 53. register 28h, ext1 measured value (power-on default 00h) bit name r/ w description 7C0 ext1 value r this register contains the measured value of the ext1 temp channel. table 54. register 29h, ext2/a in9 measured value (power-on default 00h) bit name r/ w description 7C0 ext2 temp/ a in9 low limit r this register contains the measured value of the ext2 temp/a in9 channel depending on which bit is configured.
adm1026 rev. a | page 48 of 56 table 55. register 2ah, 3.3 v stby measured value (power-on default 00h) bit name r/ w description 7C0 3.3 v stby value r this register contains the measured value of the 3.3 v stby voltage. table 56. register 2bh, 3.3 v main measured value (power-on default 00h) bit name r/ w description 7C0 3.3 v main value r this register contains th e measured value of the 3.3 v main voltage. table 57. register 2ch, +5 v measured value (power-on default 00h) bit name r/ w description 7C0 +5 v value r this register contains the meas ured value of the +5 v analog input channel. table 58. register 2dh, vccp measured value (power-on default 00h) bit name r/ w description 7C0 v ccp value r this register contains the measured value of the v ccp analog input channel. table 59. register 2eh, +12v measured value (power-on default 00h) bit name r/ w description 7C0 +12 v value r this register contains the meas ured value of the +12 v analog input channel. table 60. register 2fh, C12v measured value (power-on default 00h) bit name r/ w description 7C0 C12 v value r this register contains the measured value of the ? 12 v analog input channel. table 61. register 30h, a in0 measured value (power-on default 00h) bit name r/ w description 7C0 a in0 value r this register contains the measured value of the a in0 analog input channel. table 62. register 31h, a in1 measured value (power-on default 00h) bit name r/ w description 7C0 a in1 value r this register contains the measured value of the a in1 analog input channel. table 63. register 32h, a in2 measured value (power-on default 00h) bit name r/ w description 7C0 a in2 value r this register contains the measured value of the a in2 analog input channel. table 64. register 33h, a in3 measured value (power-on default 00h) bit name r/ w description 7C0 a in3 value r this register contains the measured value of the a in3 analog input channel. table 65. register 34h, a in4 measured value (power-on default 00h) bit name r/ w description 7C0 a in4 value r this register contains the measured value of the a in4 analog input channel. table 66. register 35h, a in5 measured value (power-on default 00h) bit name r/ w description 7C0 a in5 value r this register contains the measured value of the a in5 analog input channel. table 67. register 36h, a in6 measured value (power-on default 00h) bit name r/ w description 7C0 a in6 value r this register contains the measured value of the a in6 analog input channel. table 68. register 37h, a in7 measured value (power-on default 00h) bit name r/ w description 7C0 a in7 value r this register contains the measured value of the a in7 analog input channel.
adm1026 rev. a | page 49 of 56 table 69. register 38h, fan0 measured value (power-on default 00h) bit name r/ w description 7C0 fan0 value r this register contains the meas ured value of the fan0 tach input channel. table 70. register 39h, fan1 measured value (power-on default 00h) bit name r/ w description 7C0 fan1 value r this register contains the meas ured value of the fan1 tach input channel. table 71. register 3ah, fan2 measured value (power-on default 00h) bit name r/ w description 7C0 fan2 value r this register contains the meas ured value of the fan2 tach input channel. table 72. register 3bh, fan3 measured value (power-on default 00h) bit name r/ w description 7C0 fan3 value r this register contains the meas ured value of the fan3 tach input channel. table 73. register 3ch, fan4 measured value (power-on default 00h) bit name r/ w description 7C0 fan4 value r this register contains the meas ured value of the fan4 tach input channel. table 74. register 3dh, fan5 measured value (power-on default 00h) bit name r/ w description 7C0 fan5 value r this register contains the meas ured value of the fan5 tach input channel. table 75. register 3eh, fan6 measured value (power-on default 00h) bit name r/ w description 7C0 fan6 value r this register contains the meas ured value of the fan6 tach input channel. table 76. register 3fh, fan7 measured value (power-on default 00h) bit name r/ w description 7C0 fan7 value r this register contains the meas ured value of the fan7 tach input channel. table 77. register 40h, ext1 high limit (power-on default 64h/100c) bit name r/ w description 7C0 ext1 high limit r/w this register contains the high l imit of the ext1 temp channel. table 78. register 41h, ext2/a in9 high limit (power-on default 64h/100c) bit name r/ w description 7C0 ext2 temp/ a in9 high limit r/w this register contains the high limit of the ext2 temp/a in9 channel depending on which one is configured. table 79. register 42h, 3.3 v stby high limit (power-on default ffh) bit name r/ w description 7C0 3.3 v stby high limit r/w this register contains the high limit of the 3.3 v stby analog input channel. table 80. register 43h, 3.3 v main high limit (power-on default ffh) bit name r/ w description 7C0 3.3 v main high limit r/w this register contains the high limit of the 3.3 v main analog input channel. table 81. register 44h, +5 v high limit (power-on default ffh) bit name r/ w description 7C0 +5 v high limit r/w this register contains the high limit of the +5 v analog input channel. table 82. register 45h, v ccp high limit (power-on default ffh) bit name r/ w description 7C0 v ccp high limit r/w this register contains the high limit of the v ccp analog input channel.
adm1026 rev. a | page 50 of 56 table 83. register 46h, +12 v high limit (power-on default ffh) bit name r/ w description 7C0 +12 v high limit r/w this register contains the high limit of the +12 v analog input channel. table 84. register 47h, ?12 v high limit (power-on default ffh) bit name r/ w description 7C0 ?12v high limit r/w this register contains the high limit of the ? 12 v analog input channel. table 85. register 48h, ext1 low limit (power-on default 80h) bit name r/ w description 7C0 ext1 low limit r/w this register contains the low limit of the ext1 temp channel. table 86. register 49h, ext2 / a in9 low limit (power-on-default 80h) bit name r/ w description 7C0 ext2 temp /a in9 low limit r/w this register contains the low limit of the ext2 temp/a in9 channel depending on which bit is configured. table 87. register 4ah, 3.3 v stby low limit (power-on default 00h) bit name r/ w description 7C0 3.3 v stby low limit r/w this register contains the low limit of the 3.3 v stby analog input channel. table 88. register 4bh, 3.3 v main low limit (power-on default 00h) bit name r/ w description 7C0 3.3 v main low limit r/w this register contains the low limit of the 3.3 v main analog input channel. table 89. register 4ch, +5v low limit (power-on default 00h) bit name r/ w description 7C0 0+5 v low limit r/w this register contains the low limit of the +5 v analog input channel. table 90. register 4dh, v ccp low limit (power-on default 00h) bit name r/ w description 7C0 v ccp low limit r/w this register contains the low limit of the v ccp analog input channel. table 91. register 4eh, +12v low limit (power-on default 00h) bit name r/ w description 7C0 +12 v low limit r/w this register contains the low limit of the +12 v analog input channel. table 92. register 4fh, C12v low limit (power-on default 00h) bit name r/ w description 7C0 ?12 v low limit r/w this register contains the low limit of the ? 12 v analog input channel. table 93. register 50h, a in0 high limit (power-on default ffh) bit name r/ w description 7C0 a in0 high limit r/w this register contains the high limit of the a in0 analog input channel. table 94. register 51h, a in1 high limit (power-on default ffh) bit name r/ w description 7C0 a in1 high limit r/w this register contains the high limit of the a in1 analog input channel. table 95. register 52h, a in2 high limit (power-on default ffh) bit name r/ w description 7C0 a in2 high limit r/w this register contains the high limit of the a in2 analog input channel. table 96. register 53h, a in3 high limit (power-on default ffh) bit name r/ w description 7C0 a in3 high limit r/w this register contains the high limit of the a in3 analog input channel.
adm1026 rev. a | page 51 of 56 table 97. register 54h, a in4 high limit (power-on default ffh) bit name r/ w description 7C0 a in4 high limit r/w this register contains the high limit of the a in4 analog input channel. table 98. register 55h, a in5 high limit (power-on default ffh) bit name r/ w description 7C0 a in5 high limit r/w this register co ntains the high limit of the a in5 analog input channel. table 99. register 56h, a in6 high limit (power-on default ffh) bit name r/ w description 7C0 a in6 high limit r/w this register co ntains the high limit of the a in6 analog input channel. table 100. register 57h, a in7 high limit (power-on default ffh) bit name r/ w description 7C0 a in7 high limit r/w this register contains the high limit of the a in7 analog input channel. table 101. register 58h, a in0 low limit (power-on default 00h) bit name r/ w description 7C0 a in0 low limit r/w this register contains the low limit of the a in0 analog input channel. table 102. register 59h, a in1 low limit (power-on default 00h) bit name r/ w description 7C0 a in1 low limit r/w this register contains the low limit of the a in1 analog input channel. table 103. register 5ah, a in2 low limit (power-on default 00h) bit name r/ w description 7C0 a in2 low limit r/w this register contains the low limit of the a in2 analog input channel. table 104. register 5bh, a in3 low limit (power-on default 00h) bit name r/ w description 7C0 a in3 low limit r/w this register contains the low limit of the a in3 analog input channel. table 105. register 5ch, a in4 low limit (power-on default 00h) bit name r/ w description 7C0 a in4 low limit r/w this register contains the low limit of the a in4 analog input channel. table 106. register 5dh, a in5 low limit (power-on default 00h) bit name r/ w description 7C0 a in5 low limit r/w this register contains the low limit of the a in5 analog input channel. table 107. register 5eh, a in6 low limit (power-on default 00h) bit name r/ w description 7C0 a in6 low limit r/w this register contains the low limit of the a in6 analog input channel. table 108. register 5fh, a in7 low limit (power-on default 00h) bit name r/ w description 7C0 a in7 low limit r/w this register contains the low limit of the a in7 analog input channel. table 109. register 60h, fan0 high limit (power-on default ffh) bit name r/ w description 7C0 fan0 high limit r/w this register contains the high limit of the fan0 tach channel. table 110. register 61h, fan1 high limit (power-on default ffh) bit name r/ w description 7C0 fan1 high limit r/w this register contains the high limit of the fan1 tach channel.
adm1026 rev. a | page 52 of 56 table 111. register 62h, fan2 high limit (power-on default ffh) bit name r/ w description 7C0 fan2 high limit r/w this register contains the high l imit of the fan2 tach channel. table 112. register 63h, fan3 high limit (power-on default ffh) bit name r/ w description 7C0 fan3 high limit r/w this register contains the high l imit of the fan3 tach channel. table 113. register 64h, fan4 high limit (power-on default ffh) bit name r/ w description 7C0 fan4 high limit r/w this register contains the high l imit of the fan4 tach channel. table 114. register 65h, fan5 high limit (power-on default ffh) bit name r/ w description 7C0 fan5 high limit r/w this register contains the high l imit of the fan5 tach channel. table 115. register 66h, fan6 high limit (power-on default ffh) bit name r/ w description 7C0 fan6 high limit r/w this register contains the high l imit of the fan6 tach channel. table 116. register 67h, fan7 high limit (power-on default ffh) bit name r/ w description 7C0 fan7 high limit r/w this register contains the high l imit of the fan7 tach channel. table 117. register 68h, int temp high limit (power-on default 50h (80c)) bit name r/ w description 7C0 int temp high limit r/w this register contains the high limit of the internal temperature channel. table 118. register 69h, int temp low limit (power-on default 80h) bit name r/ w description 7C0 int temp low limit r/w this register contains the low limit of the internal temperature channel. table 119. register 6ah, v bat high limit (power-on default ffh) bit name r/ w description 7C0 v bat high limit r/w this register co ntains the high limit of the v bat analog input channel. table 120. register 6bh, v bat low limit (power-on default 00h) bit name r/ w description 7C0 v bat low limit r/w this register contains the low limit of the v bat analog input channel. table 121. register 6ch, a in8 high limit (power-on default ffh) bit name r/ w description 7C0 a in8 high limit r/w this register contains the high limit of the a in8 analog input channel. table 122. register 6dh, ain8 low limit (power-on default 00h) bit name r/ w description 7C0 a in8 low limit r/w this register contains the low limit of the a in8 analog input channel.
adm1026 rev. a | page 53 of 56 table 123. register 6eh, ext1 temp offset (power-on default 00h) bit name r/ w description 7C0 ext1 temp offset r/w this register contains the offset value for the external 1 temperature cha nnel. a twos complement number can be written to this register, which is then added to the measured result before it is stored or compared to limits. in this way, a sort of one-point calibration can be done whereby the whole transfer function of the channel can be moved up or down. from a software point of view, this may be a very simple method to vary the characteristics of the measurement channel if the thermal characteristics change for any reason (for instance from one chassis to another), if the measurement point is moved, if a plug-in ca rd is inserted or removed, and so on. table 124. register 6fh, ext2 temp offset (power-on default 00h) bit name r/ w description 7C0 ext2 temp offset r/w this register contains the offset value for the external 2 temperature cha nnel. a twos complement number can be written to this register, which is then added to the measured result before it is stored or compared to limits. in this way, a sort of one-point calibration can be done whereby the whole transfer function of the channel can be moved up or down. from a software point of view, this may be a very simple method to vary the characteristics of the measurement channel if the thermal characteristics change for any reason (for instance from one chassis to another), if the measurement point is moved, if a plug-in ca rd is inserted or removed, and so on.
adm1026 rev. a | page 54 of 56 outline dimensions top view (pins down) 1 12 13 25 24 36 37 48 0.27 0.22 0.17 0.50 bsc 7.00 bsc sq seating plane 1.60 max 0.75 0.60 0.45 view a 9.00 bsc sq pin 1 0.20 0.09 1.45 1.40 1.35 0.08 max coplanarity view a rotated 90 ccw seating plane 10 6 2 7 3.5 0 0.15 0.05 compliant to jedec standards ms-026bbc figure 63. 48-lead thin plastic quad flat package [lqfp] 7 mm x 7 mm x 1.4 mm thick (st-48) dimensions shown in millimeters
adm1026 rev. a | page 55 of 56 ordering guide model temperature range package description package option ADM1026JST 0c to 100c 48-lead lqfp st-48 ADM1026JST-reel 0c to 100c 48-lead lqfp st-48 ADM1026JST-reel7 0c to 100c 48-lead lqfp st-48 ADM1026JSTz-reel 1 0c to 100c 48-lead lqfp st-48 eval-adm1026eb evaluation board 1 z = pb-free part.
adm1026 rev. a | page 56 of 56 notes ? 2004 analog devices, inc. all rights reserved. trademarks and registered trademarks are the proper ty of their respective owners. c02657-0-3/04(a)

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